DE69514450D1 - Prüfung eines nichtflüchtigen Speichers - Google Patents

Prüfung eines nichtflüchtigen Speichers

Info

Publication number
DE69514450D1
DE69514450D1 DE69514450T DE69514450T DE69514450D1 DE 69514450 D1 DE69514450 D1 DE 69514450D1 DE 69514450 T DE69514450 T DE 69514450T DE 69514450 T DE69514450 T DE 69514450T DE 69514450 D1 DE69514450 D1 DE 69514450D1
Authority
DE
Germany
Prior art keywords
volatile memory
check non
check
volatile
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69514450T
Other languages
English (en)
Other versions
DE69514450T2 (de
Inventor
Vijay Malhi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Ltd filed Critical STMicroelectronics Ltd Great Britain
Publication of DE69514450D1 publication Critical patent/DE69514450D1/de
Application granted granted Critical
Publication of DE69514450T2 publication Critical patent/DE69514450T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
DE69514450T 1994-08-26 1995-08-21 Prüfung eines nichtflüchtigen Speichers Expired - Fee Related DE69514450T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9417266A GB9417266D0 (en) 1994-08-26 1994-08-26 Testing a non-volatile memory

Publications (2)

Publication Number Publication Date
DE69514450D1 true DE69514450D1 (de) 2000-02-17
DE69514450T2 DE69514450T2 (de) 2000-06-08

Family

ID=10760449

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69514450T Expired - Fee Related DE69514450T2 (de) 1994-08-26 1995-08-21 Prüfung eines nichtflüchtigen Speichers

Country Status (4)

Country Link
US (1) US5627780A (de)
EP (1) EP0698891B1 (de)
DE (1) DE69514450T2 (de)
GB (1) GB9417266D0 (de)

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* Cited by examiner, † Cited by third party
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DE69529367T2 (de) * 1994-08-19 2004-01-22 Kabushiki Kaisha Toshiba, Kawasaki Halbleiterspeicheranordnung und hochspannungsschaltende Schaltung
GB9417269D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Memory and test method therefor
FR2735896B1 (fr) * 1995-06-21 1997-08-22 Sgs Thomson Microelectronics Memoire eeprom programmable et effacable par effet de fowler-nordheim
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US6335878B1 (en) * 1998-07-28 2002-01-01 Hitachi, Ltd. Non-volatile multi-level semiconductor flash memory device and method of driving same
US5872736A (en) * 1996-10-28 1999-02-16 Micron Technology, Inc. High speed input buffer
US5917758A (en) * 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US5949254A (en) * 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5920518A (en) * 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US5956502A (en) * 1997-03-05 1999-09-21 Micron Technology, Inc. Method and circuit for producing high-speed counts
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US5870347A (en) 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
US6014759A (en) * 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US5926047A (en) 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US6101197A (en) * 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US5923594A (en) * 1998-02-17 1999-07-13 Micron Technology, Inc. Method and apparatus for coupling data from a memory device using a single ended read data path
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6349399B1 (en) * 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6115303A (en) 1998-10-09 2000-09-05 Micron Technology, Inc. Method and apparatus for testing memory devices
JP2000156095A (ja) * 1998-11-19 2000-06-06 Asia Electronics Inc 半導体メモリ試験方法及びその装置
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
US6799290B1 (en) * 2000-02-25 2004-09-28 Infineon Technologies North America Corp Data path calibration and testing mode using a data bus for semiconductor memories
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7168027B2 (en) * 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7881127B2 (en) * 2008-05-20 2011-02-01 Hynix Semiconductor Inc. Nonvolatile memory device and method of testing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040745B1 (de) * 1970-06-22 1975-12-26
US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US4227244A (en) * 1978-11-30 1980-10-07 Sperry Corporation Closed loop address
US5175840A (en) * 1985-10-02 1992-12-29 Hitachi, Ltd. Microcomputer having a PROM including data security and test circuitry
JPH0589687A (ja) * 1991-09-27 1993-04-09 Nec Corp 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
EP0698891A1 (de) 1996-02-28
EP0698891B1 (de) 2000-01-12
US5627780A (en) 1997-05-06
GB9417266D0 (en) 1994-10-19
DE69514450T2 (de) 2000-06-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee