DE69417281D1 - Verfahren und Schaltung zur Verbesserung von Steuerzeit- und Störabstand in einem DRAM Speicher - Google Patents

Verfahren und Schaltung zur Verbesserung von Steuerzeit- und Störabstand in einem DRAM Speicher

Info

Publication number
DE69417281D1
DE69417281D1 DE69417281T DE69417281T DE69417281D1 DE 69417281 D1 DE69417281 D1 DE 69417281D1 DE 69417281 T DE69417281 T DE 69417281T DE 69417281 T DE69417281 T DE 69417281T DE 69417281 D1 DE69417281 D1 DE 69417281D1
Authority
DE
Germany
Prior art keywords
timing
improving
circuit
signal
noise ratio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69417281T
Other languages
English (en)
Other versions
DE69417281T2 (de
Inventor
Oscar Frederick Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UMC Japan Co Ltd
United Memories Inc
Original Assignee
Nippon Steel Semiconductor Corp
United Memories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Semiconductor Corp, United Memories Inc filed Critical Nippon Steel Semiconductor Corp
Publication of DE69417281D1 publication Critical patent/DE69417281D1/de
Application granted granted Critical
Publication of DE69417281T2 publication Critical patent/DE69417281T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
DE69417281T 1993-03-26 1994-02-23 Verfahren und Schaltung zur Verbesserung von Steuerzeit- und Störabstand in einem DRAM Speicher Expired - Fee Related DE69417281T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/037,288 US5379261A (en) 1993-03-26 1993-03-26 Method and circuit for improved timing and noise margin in a DRAM

Publications (2)

Publication Number Publication Date
DE69417281D1 true DE69417281D1 (de) 1999-04-29
DE69417281T2 DE69417281T2 (de) 1999-11-04

Family

ID=21893527

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69417281T Expired - Fee Related DE69417281T2 (de) 1993-03-26 1994-02-23 Verfahren und Schaltung zur Verbesserung von Steuerzeit- und Störabstand in einem DRAM Speicher

Country Status (4)

Country Link
US (1) US5379261A (de)
EP (1) EP0618588B1 (de)
JP (1) JP3224678B2 (de)
DE (1) DE69417281T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574866A (en) * 1993-04-05 1996-11-12 Zenith Data Systems Corporation Method and apparatus for providing a data write signal with a programmable duration
US6804760B2 (en) 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5729503A (en) * 1994-12-23 1998-03-17 Micron Technology, Inc. Address transition detection on a synchronous design
US5721859A (en) * 1994-12-23 1998-02-24 Micron Technology, Inc. Counter control circuit in a burst memory
US5640364A (en) * 1994-12-23 1997-06-17 Micron Technology, Inc. Self-enabling pulse trapping circuit
US5668773A (en) * 1994-12-23 1997-09-16 Micron Technology, Inc. Synchronous burst extended data out DRAM
US6525971B2 (en) * 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5682354A (en) * 1995-11-06 1997-10-28 Micron Technology, Inc. CAS recognition in burst extended data out DRAM
US5675549A (en) * 1994-12-23 1997-10-07 Micron Technology, Inc. Burst EDO memory device address counter
US5717654A (en) * 1995-02-10 1998-02-10 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5544124A (en) * 1995-03-13 1996-08-06 Micron Technology, Inc. Optimization circuitry and control for a synchronous memory device with programmable latency period
US5850368A (en) * 1995-06-01 1998-12-15 Micron Technology, Inc. Burst EDO memory address counter
US5546344A (en) * 1995-06-06 1996-08-13 Cirrus Logic, Inc. Extended data output DRAM interface
KR0157289B1 (ko) * 1995-11-13 1998-12-01 김광호 컬럼 선택 신호 제어회로
US5729504A (en) * 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
US5966724A (en) * 1996-01-11 1999-10-12 Micron Technology, Inc. Synchronous memory device with dual page and burst mode operations
US7681005B1 (en) * 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
US6981126B1 (en) * 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US5708613A (en) * 1996-07-22 1998-01-13 International Business Machines Corporation High performance redundancy in an integrated memory system
US5793698A (en) * 1996-09-06 1998-08-11 Creative Integrated Systems, Inc. Semiconductor read-only VLSI memory
KR100302424B1 (ko) * 1996-10-14 2001-09-28 니시무로 타이죠 논리하이브리드메모리용반도체메모리
US6567336B2 (en) * 1996-10-14 2003-05-20 Kabushiki Kaisha Toshiba Semiconductor memory for logic-hybrid memory
KR100231605B1 (ko) * 1996-12-31 1999-11-15 김영환 반도체 메모리 소자의 전력소모 방지 장치
US7103742B1 (en) 1997-12-03 2006-09-05 Micron Technology, Inc. Burst/pipelined edo memory device
US7131033B1 (en) 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US6990010B1 (en) * 2003-08-06 2006-01-24 Actel Corporation Deglitching circuits for a radiation-hardened static random access memory based programmable architecture
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212690A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Dynamic mos memory device
US4750839A (en) * 1985-08-07 1988-06-14 Texas Instruments Incorporated Semiconductor memory with static column decode and page mode addressing capability
JP2569554B2 (ja) * 1987-05-13 1997-01-08 三菱電機株式会社 ダイナミツクｒａｍ
JPH01205788A (ja) * 1988-02-12 1989-08-18 Toshiba Corp 半導体集積回路
US5280601A (en) * 1990-03-02 1994-01-18 Seagate Technology, Inc. Buffer memory control system for a magnetic disc controller
US5077693A (en) * 1990-08-06 1991-12-31 Motorola, Inc. Dynamic random access memory

Also Published As

Publication number Publication date
EP0618588B1 (de) 1999-03-24
US5379261A (en) 1995-01-03
JPH06295583A (ja) 1994-10-21
EP0618588A2 (de) 1994-10-05
DE69417281T2 (de) 1999-11-04
JP3224678B2 (ja) 2001-11-05
EP0618588A3 (de) 1994-10-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee