DE69416225D1 - Verfahren zur Trockenätzung - Google Patents

Verfahren zur Trockenätzung

Info

Publication number
DE69416225D1
DE69416225D1 DE69416225T DE69416225T DE69416225D1 DE 69416225 D1 DE69416225 D1 DE 69416225D1 DE 69416225 T DE69416225 T DE 69416225T DE 69416225 T DE69416225 T DE 69416225T DE 69416225 D1 DE69416225 D1 DE 69416225D1
Authority
DE
Germany
Prior art keywords
dry etching
etching method
dry
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69416225T
Other languages
English (en)
Other versions
DE69416225T2 (de
Inventor
Kadomura Shingo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE69416225D1 publication Critical patent/DE69416225D1/de
Publication of DE69416225T2 publication Critical patent/DE69416225T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
DE69416225T 1993-09-13 1994-09-13 Verfahren zur Trockenätzung Expired - Fee Related DE69416225T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5227132A JPH0786244A (ja) 1993-09-13 1993-09-13 ドライエッチング方法

Publications (2)

Publication Number Publication Date
DE69416225D1 true DE69416225D1 (de) 1999-03-11
DE69416225T2 DE69416225T2 (de) 1999-08-19

Family

ID=16855984

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69416225T Expired - Fee Related DE69416225T2 (de) 1993-09-13 1994-09-13 Verfahren zur Trockenätzung

Country Status (5)

Country Link
US (1) US5994226A (de)
EP (1) EP0644582B1 (de)
JP (1) JPH0786244A (de)
KR (1) KR100272644B1 (de)
DE (1) DE69416225T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3334370B2 (ja) * 1994-10-13 2002-10-15 ヤマハ株式会社 半導体デバイス
US6541164B1 (en) * 1997-10-22 2003-04-01 Applied Materials, Inc. Method for etching an anti-reflective coating
US6013582A (en) * 1997-12-08 2000-01-11 Applied Materials, Inc. Method for etching silicon oxynitride and inorganic antireflection coatings
US6291356B1 (en) 1997-12-08 2001-09-18 Applied Materials, Inc. Method for etching silicon oxynitride and dielectric antireflection coatings
DE10000004A1 (de) * 2000-01-03 2001-05-17 Infineon Technologies Ag Verfahren zur Herstellung von Leitbahnen
US6762129B2 (en) * 2000-04-19 2004-07-13 Matsushita Electric Industrial Co., Ltd. Dry etching method, fabrication method for semiconductor device, and dry etching apparatus
DE10054969A1 (de) * 2000-11-06 2002-03-28 Infineon Technologies Ag Verfahren zur Strukturierung von Metallschichten
US6569778B2 (en) * 2001-06-28 2003-05-27 Hynix Semiconductor Inc. Method for forming fine pattern in semiconductor device
CN100451831C (zh) * 2001-10-29 2009-01-14 旺宏电子股份有限公司 减小图案间隙或开口尺寸的方法
US6573177B1 (en) * 2002-02-19 2003-06-03 Macronix International Co., Ltd. Protection layer to prevent under-layer damage during deposition
US7473377B2 (en) 2002-06-27 2009-01-06 Tokyo Electron Limited Plasma processing method
KR100619398B1 (ko) * 2003-12-26 2006-09-11 동부일렉트로닉스 주식회사 반사방지막을 구비한 레티클 제조방법
US7291563B2 (en) * 2005-08-18 2007-11-06 Micron Technology, Inc. Method of etching a substrate; method of forming a feature on a substrate; and method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate
JP4630795B2 (ja) * 2005-10-26 2011-02-09 株式会社東芝 パターン形成方法および磁気記録媒体の製造方法
US7579282B2 (en) * 2006-01-13 2009-08-25 Freescale Semiconductor, Inc. Method for removing metal foot during high-k dielectric/metal gate etching
US8233248B1 (en) 2009-09-16 2012-07-31 Western Digital (Fremont), Llc Method and system for providing a magnetic recording transducer using a line hard mask
US8871102B2 (en) 2011-05-25 2014-10-28 Western Digital (Fremont), Llc Method and system for fabricating a narrow line structure in a magnetic recording head
US8518832B1 (en) 2011-06-27 2013-08-27 Western Digital (Fremont), Llc Process for masking and removal of residue from complex shapes
US8703397B1 (en) 2012-03-29 2014-04-22 Western Digital (Fremont), Llc Method for providing side shields for a magnetic recording transducer
US9034564B1 (en) 2013-07-26 2015-05-19 Western Digital (Fremont), Llc Reader fabrication method employing developable bottom anti-reflective coating
US9001467B1 (en) 2014-03-05 2015-04-07 Western Digital (Fremont), Llc Method for fabricating side shields in a magnetic writer
US9583356B1 (en) 2015-09-30 2017-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor device structure
CN107104044A (zh) * 2017-05-12 2017-08-29 京东方科技集团股份有限公司 一种电极制作方法及阵列基板的制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181378A (en) * 1981-04-30 1982-11-08 Toshiba Corp Dry etching method
DE68923247T2 (de) * 1988-11-04 1995-10-26 Fujitsu Ltd Verfahren zum Erzeugen eines Fotolackmusters.
JPH03110846A (ja) * 1989-09-25 1991-05-10 Sony Corp 配線の形成方法
JPH03156927A (ja) * 1989-10-24 1991-07-04 Hewlett Packard Co <Hp> アルミ・メタライゼーションのパターン形成方法
JP3170791B2 (ja) * 1990-09-11 2001-05-28 ソニー株式会社 Ａｌ系材料膜のエッチング方法
JPH04125924A (ja) * 1990-09-17 1992-04-27 Mitsubishi Electric Corp プラズマエッチング方法
JPH04142738A (ja) * 1990-10-04 1992-05-15 Sony Corp ドライエッチング方法
JP3094470B2 (ja) * 1991-01-22 2000-10-03 ソニー株式会社 ドライエッチング方法
JPH04330724A (ja) * 1991-01-28 1992-11-18 Sony Corp 配線形成方法
US5217570A (en) * 1991-01-31 1993-06-08 Sony Corporation Dry etching method
JPH04288828A (ja) * 1991-03-18 1992-10-13 Sony Corp ドライエッチング方法
JP3371143B2 (ja) * 1991-06-03 2003-01-27 ソニー株式会社 ドライエッチング方法
JP3198586B2 (ja) * 1992-02-14 2001-08-13 ソニー株式会社 ドライエッチング方法
JP3181741B2 (ja) * 1993-01-11 2001-07-03 富士通株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR100272644B1 (ko) 2000-12-01
KR950009963A (ko) 1995-04-26
EP0644582B1 (de) 1999-01-27
US5994226A (en) 1999-11-30
JPH0786244A (ja) 1995-03-31
DE69416225T2 (de) 1999-08-19
EP0644582A2 (de) 1995-03-22
EP0644582A3 (de) 1996-03-20

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee