DE69332496T2 - Verfahren zur Dielektrikim-Entfernung - Google Patents

Verfahren zur Dielektrikim-Entfernung

Info

Publication number
DE69332496T2
DE69332496T2 DE1993632496 DE69332496T DE69332496T2 DE 69332496 T2 DE69332496 T2 DE 69332496T2 DE 1993632496 DE1993632496 DE 1993632496 DE 69332496 T DE69332496 T DE 69332496T DE 69332496 T2 DE69332496 T2 DE 69332496T2
Authority
DE
Grant status
Grant
Patent type
Prior art keywords
dielektrikim
removal
process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE1993632496
Other languages
English (en)
Other versions
DE69332496D1 (de )
Inventor
Steven C Hall
Mark I Gardner
Fulford, Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/911Differential oxidation and etching
DE1993632496 1992-09-18 1993-07-01 Verfahren zur Dielektrikim-Entfernung Expired - Lifetime DE69332496T2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US07947314 US5350492A (en) 1992-09-18 1992-09-18 Oxide removal method for improvement of subsequently grown oxides

Publications (1)

Publication Number Publication Date
DE69332496T2 true DE69332496T2 (de) 2003-10-09

Family

ID=25485943

Family Applications (2)

Application Number Title Priority Date Filing Date
DE1993632496 Expired - Lifetime DE69332496D1 (de) 1992-09-18 1993-07-01 Verfahren zur Dielektrikim-Entfernung
DE1993632496 Expired - Lifetime DE69332496T2 (de) 1992-09-18 1993-07-01 Verfahren zur Dielektrikim-Entfernung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE1993632496 Expired - Lifetime DE69332496D1 (de) 1992-09-18 1993-07-01 Verfahren zur Dielektrikim-Entfernung

Country Status (4)

Country Link
US (1) US5350492A (de)
EP (1) EP0592071B1 (de)
JP (1) JPH06204203A (de)
DE (2) DE69332496D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3006387B2 (ja) * 1993-12-15 2000-02-07 日本電気株式会社 半導体装置およびその製造方法
US5858843A (en) * 1996-09-27 1999-01-12 Intel Corporation Low temperature method of forming gate electrode and gate dielectric
JP2001525612A (ja) * 1997-11-28 2001-12-11 アリゾナ ボード オブ リージェンツ、アクティング オン ビハーフ オブ アリゾナ ステイト ユニバーシティ Si、SixGe1−x、GaAsおよび他の半導体上で、長距離に配列された、SiO2含有エピタキシャル酸化物、材料合成とその応用
US7273266B2 (en) * 2004-04-14 2007-09-25 Lexmark International, Inc. Micro-fluid ejection assemblies
US9159808B2 (en) * 2009-01-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Selective etch-back process for semiconductor devices
WO2010127320A3 (en) 2009-04-30 2011-01-13 Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University Methods for wafer bonding, and for nucleating bonding nanophases
US9589801B2 (en) 2011-10-31 2017-03-07 Arizona Board Of Regents, A Body Corporated Of The State Of Arizona, Acting For And On Behalf Of Arizona State University Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization
WO2014052476A3 (en) 2012-09-25 2014-06-26 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On... Methods for wafer bonding, and for nucleating bonding nanophases

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US4539744A (en) * 1984-02-03 1985-09-10 Fairchild Camera & Instrument Corporation Semiconductor planarization process and structures made thereby
US4713329A (en) * 1985-07-22 1987-12-15 Data General Corporation Well mask for CMOS process
US4713307A (en) * 1986-04-11 1987-12-15 Xerox Corporation Organic azo photoconductor imaging members
JPH0272661A (en) * 1988-09-07 1990-03-12 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH088298B2 (ja) * 1988-10-04 1996-01-29 沖電気工業株式会社 半導体素子の製造方法

Also Published As

Publication number Publication date Type
JPH06204203A (ja) 1994-07-22 application
EP0592071A3 (en) 1997-10-08 application
EP0592071A2 (de) 1994-04-13 application
US5350492A (en) 1994-09-27 grant
DE69332496D1 (de) 2003-01-02 grant
EP0592071B1 (de) 2002-11-20 grant

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