DE69318330D1 - Speicher mit Spaltenredundanz und mit örtlich begrenzten Spaltenredundanzsteuersignalen - Google Patents

Speicher mit Spaltenredundanz und mit örtlich begrenzten Spaltenredundanzsteuersignalen

Info

Publication number
DE69318330D1
DE69318330D1 DE69318330T DE69318330T DE69318330D1 DE 69318330 D1 DE69318330 D1 DE 69318330D1 DE 69318330 T DE69318330 T DE 69318330T DE 69318330 T DE69318330 T DE 69318330T DE 69318330 D1 DE69318330 D1 DE 69318330D1
Authority
DE
Germany
Prior art keywords
redundant
column redundancy
read
write
global data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69318330T
Other languages
English (en)
Other versions
DE69318330T2 (de
Inventor
Taisheng Feng
Stephen Flannagan
John David Porter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69318330D1 publication Critical patent/DE69318330D1/de
Publication of DE69318330T2 publication Critical patent/DE69318330T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
DE69318330T 1992-03-02 1993-02-23 Speicher mit Spaltenredundanz und mit örtlich begrenzten Spaltenredundanzsteuersignalen Expired - Fee Related DE69318330T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/844,022 US5268866A (en) 1992-03-02 1992-03-02 Memory with column redundancy and localized column redundancy control signals

Publications (2)

Publication Number Publication Date
DE69318330D1 true DE69318330D1 (de) 1998-06-10
DE69318330T2 DE69318330T2 (de) 1998-12-03

Family

ID=25291576

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69318330T Expired - Fee Related DE69318330T2 (de) 1992-03-02 1993-02-23 Speicher mit Spaltenredundanz und mit örtlich begrenzten Spaltenredundanzsteuersignalen

Country Status (6)

Country Link
US (1) US5268866A (de)
EP (1) EP0559368B1 (de)
JP (1) JPH0644796A (de)
KR (1) KR100276373B1 (de)
DE (1) DE69318330T2 (de)
SG (1) SG45264A1 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950004623B1 (ko) * 1992-12-07 1995-05-03 삼성전자주식회사 리던던시 효율이 향상되는 반도체 메모리 장치
DE69412234T2 (de) * 1994-03-29 1999-06-17 Sgs Thomson Microelectronics Redundanzschaltung für eine Halbleiter-Speicheranordnung
US5528539A (en) * 1994-09-29 1996-06-18 Micron Semiconductor, Inc. High speed global row redundancy system
US6108237A (en) 1997-07-17 2000-08-22 Micron Technology, Inc. Fast-sensing amplifier for flash memory
ATE218003T1 (de) * 1995-02-10 2002-06-15 Micron Technology Inc Schneller leseverstärker für einen flash-speicher
US5627786A (en) * 1995-02-10 1997-05-06 Micron Quantum Devices, Inc. Parallel processing redundancy scheme for faster access times and lower die area
GB2312974A (en) * 1996-05-10 1997-11-12 Memory Corp Plc Memory replacement
US5673227A (en) * 1996-05-14 1997-09-30 Motorola, Inc. Integrated circuit memory with multiplexed redundant column data path
US5691946A (en) * 1996-12-03 1997-11-25 International Business Machines Corporation Row redundancy block architecture
US5841710A (en) * 1997-02-14 1998-11-24 Micron Electronics, Inc. Dynamic address remapping decoder
US6058052A (en) * 1997-08-21 2000-05-02 Cypress Semiconductor Corp. Redundancy scheme providing improvements in redundant circuit access time and integrated circuit layout area
US6005813A (en) * 1997-11-12 1999-12-21 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6332183B1 (en) 1998-03-05 2001-12-18 Micron Technology, Inc. Method for recovery of useful areas of partially defective synchronous memory components
US6314527B1 (en) 1998-03-05 2001-11-06 Micron Technology, Inc. Recovery of useful areas of partially defective synchronous memory components
US6381707B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. System for decoding addresses for a defective memory array
US6381708B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. Method for decoding addresses for a defective memory array
US6137735A (en) * 1998-10-30 2000-10-24 Mosaid Technologies Incorporated Column redundancy circuit with reduced signal path delay
US6496876B1 (en) 1998-12-21 2002-12-17 Micron Technology, Inc. System and method for storing a tag to identify a functional storage location in a memory device
JP4950816B2 (ja) * 1999-06-03 2012-06-13 株式会社東芝 半導体メモリ
KR100443527B1 (ko) * 1999-06-30 2004-08-09 주식회사 하이닉스반도체 로오 리던던시 회로
JP2001084791A (ja) 1999-07-12 2001-03-30 Mitsubishi Electric Corp 半導体記憶装置
US6144593A (en) * 1999-09-01 2000-11-07 Micron Technology, Inc. Circuit and method for a multiplexed redundancy scheme in a memory device
US6578157B1 (en) 2000-03-06 2003-06-10 Micron Technology, Inc. Method and apparatus for recovery of useful areas of partially defective direct rambus rimm components
US7269765B1 (en) 2000-04-13 2007-09-11 Micron Technology, Inc. Method and apparatus for storing failing part locations in a module
JP5119563B2 (ja) * 2001-08-03 2013-01-16 日本電気株式会社 不良メモリセル救済回路を有する半導体記憶装置
WO2003038834A1 (en) * 2001-10-31 2003-05-08 Mosaid Technologies Incorporated Column redundancy for content addressable memory
CA2360897C (en) 2001-10-31 2011-01-25 Mosaid Technologies Incorporated Column redundancy for content addressable memory
US6879530B2 (en) * 2002-07-18 2005-04-12 Micron Technology, Inc. Apparatus for dynamically repairing a semiconductor memory
JP2004063023A (ja) * 2002-07-30 2004-02-26 Renesas Technology Corp 半導体記憶装置
KR100490084B1 (ko) * 2002-09-12 2005-05-17 삼성전자주식회사 효율적인 리던던시 구제율을 갖는 반도체 메모리 장치
JP2004110870A (ja) * 2002-09-13 2004-04-08 Fujitsu Ltd 半導体記憶装置
US6992937B2 (en) * 2003-07-28 2006-01-31 Silicon Storage Technology, Inc. Column redundancy for digital multilevel nonvolatile memory
KR100530930B1 (ko) * 2004-05-11 2005-11-23 주식회사 하이닉스반도체 낸드 플래시 메모리 장치의 멀티-ｉ/ｏ 리페어 방법 및그의 낸드 플래시 메모리 장치
US7215586B2 (en) * 2005-06-29 2007-05-08 Micron Technology, Inc. Apparatus and method for repairing a semiconductor memory
JP2011159345A (ja) * 2010-01-29 2011-08-18 Elpida Memory Inc 半導体記憶装置
KR20120122594A (ko) * 2011-04-29 2012-11-07 에스케이하이닉스 주식회사 반도체 장치
US9348694B1 (en) * 2013-10-09 2016-05-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
US10073735B1 (en) 2014-10-28 2018-09-11 Seagate Technology Llc Seeding mechanism for error detection codes

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199999A (ja) * 1984-10-19 1986-05-19 Hitachi Ltd 半導体記憶装置
US4807191A (en) * 1988-01-04 1989-02-21 Motorola, Inc. Redundancy for a block-architecture memory
US5134584A (en) * 1988-07-22 1992-07-28 Vtc Incorporated Reconfigurable memory
US5126973A (en) * 1990-02-14 1992-06-30 Texas Instruments Incorporated Redundancy scheme for eliminating defects in a memory device

Also Published As

Publication number Publication date
EP0559368A2 (de) 1993-09-08
US5268866A (en) 1993-12-07
JPH0644796A (ja) 1994-02-18
DE69318330T2 (de) 1998-12-03
SG45264A1 (en) 1998-01-16
KR930020476A (ko) 1993-10-19
KR100276373B1 (ko) 2001-01-15
EP0559368A3 (de) 1994-04-27
EP0559368B1 (de) 1998-05-06

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee