DE69132951D1 - Halbleiter-speicher-vorrichtung - Google Patents

Halbleiter-speicher-vorrichtung

Info

Publication number
DE69132951D1
DE69132951D1 DE69132951T DE69132951T DE69132951D1 DE 69132951 D1 DE69132951 D1 DE 69132951D1 DE 69132951 T DE69132951 T DE 69132951T DE 69132951 T DE69132951 T DE 69132951T DE 69132951 D1 DE69132951 D1 DE 69132951D1
Authority
DE
Germany
Prior art keywords
wla
storage device
semiconductor storage
activated
word line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69132951T
Other languages
English (en)
Other versions
DE69132951T2 (de
Inventor
Sampei Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69132951D1 publication Critical patent/DE69132951D1/de
Application granted granted Critical
Publication of DE69132951T2 publication Critical patent/DE69132951T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69132951T 1991-08-28 1991-08-28 Halbleiter-speicher-vorrichtung Expired - Lifetime DE69132951T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1991/001142 WO1993005512A1 (en) 1991-08-28 1991-08-28 Semiconductor storage device

Publications (2)

Publication Number Publication Date
DE69132951D1 true DE69132951D1 (de) 2002-04-18
DE69132951T2 DE69132951T2 (de) 2002-09-12

Family

ID=14014577

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132951T Expired - Lifetime DE69132951T2 (de) 1991-08-28 1991-08-28 Halbleiter-speicher-vorrichtung

Country Status (5)

Country Link
US (1) US5394368A (de)
EP (2) EP1227504B1 (de)
KR (1) KR100251036B1 (de)
DE (1) DE69132951T2 (de)
WO (1) WO1993005512A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0152168B1 (ko) * 1994-04-15 1998-10-01 모리시다 요이치 반도체 기억장치
EP0728359B1 (de) * 1994-09-13 2002-05-22 Macronix International Co., Ltd. Flash-eprom-integrierte schaltungsarchitektur
KR0157344B1 (ko) * 1995-05-25 1998-12-01 김광호 반도체 메모리 장치의 퓨즈소자 회로
US5691945A (en) * 1995-05-31 1997-11-25 Macronix International Co., Ltd. Technique for reconfiguring a high density memory
JP3557019B2 (ja) * 1995-11-17 2004-08-25 株式会社東芝 半導体記憶装置
JP3501893B2 (ja) * 1996-02-23 2004-03-02 株式会社 沖マイクロデザイン 半導体記憶装置
KR100231137B1 (ko) * 1996-12-28 1999-11-15 문정환 반도체 메모리의 워드 라인 구동 회로
CA2202692C (en) * 1997-04-14 2006-06-13 Mosaid Technologies Incorporated Column redundancy in semiconductor memories
US6518945B1 (en) 1997-07-25 2003-02-11 Aurora Systems, Inc. Replacing defective circuit elements by column and row shifting in a flat-panel display
US6137735A (en) * 1998-10-30 2000-10-24 Mosaid Technologies Incorporated Column redundancy circuit with reduced signal path delay
US6496427B2 (en) * 2000-08-28 2002-12-17 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device
JP4184586B2 (ja) 2000-09-28 2008-11-19 株式会社東芝 半導体記憶装置
KR100356803B1 (ko) * 2000-11-23 2002-10-18 주식회사 하이닉스반도체 컬럼 리페어 회로
US20060274585A1 (en) * 2005-06-03 2006-12-07 Jung Chang H Memory device with row shifting for defective row repair
JP4865302B2 (ja) * 2005-11-11 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20190019568A1 (en) * 2017-07-12 2019-01-17 Nanya Technology Corporation Fuse-blowing system and method for operating the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4346459A (en) * 1980-06-30 1982-08-24 Inmos Corporation Redundancy scheme for an MOS memory
JPS57208694A (en) * 1981-06-16 1982-12-21 Nippon Telegr & Teleph Corp <Ntt> Switching system of storage cell array
JPS60109099A (ja) * 1983-11-18 1985-06-14 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ装置の欠陥検出切替方式
GB2154032B (en) * 1984-02-08 1988-04-20 Inmos Ltd A repairable memory array
JPS6161300A (ja) * 1984-09-03 1986-03-29 Hitachi Ltd 欠陥救済回路
JPS63142599A (ja) * 1986-12-05 1988-06-14 Sony Corp メモリ装置における不良セルの置換方法
JPH073754B2 (ja) * 1988-03-08 1995-01-18 三菱電機株式会社 半導体記憶装置
KR910005601B1 (ko) * 1989-05-24 1991-07-31 삼성전자주식회사 리던던트 블럭을 가지는 반도체 메모리장치
JP2837433B2 (ja) * 1989-06-05 1998-12-16 三菱電機株式会社 半導体記憶装置における不良ビット救済回路

Also Published As

Publication number Publication date
EP0554453A4 (en) 1996-09-11
EP1227504A3 (de) 2003-01-29
EP1227504B1 (de) 2004-08-04
EP0554453A1 (de) 1993-08-11
DE69132951T2 (de) 2002-09-12
KR100251036B1 (en) 2000-05-01
EP1227504A2 (de) 2002-07-31
WO1993005512A1 (en) 1993-03-18
US5394368A (en) 1995-02-28
EP0554453B1 (de) 2002-03-13
KR930702760A (ko) 1993-09-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP