DE69121047T2 - Ätzverfahren für Materialien aus Oxid - Google Patents

Ätzverfahren für Materialien aus Oxid

Info

Publication number
DE69121047T2
DE69121047T2 DE69121047T DE69121047T DE69121047T2 DE 69121047 T2 DE69121047 T2 DE 69121047T2 DE 69121047 T DE69121047 T DE 69121047T DE 69121047 T DE69121047 T DE 69121047T DE 69121047 T2 DE69121047 T2 DE 69121047T2
Authority
DE
Germany
Prior art keywords
etching
gas
layer
substrate
chf3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69121047T
Other languages
German (de)
English (en)
Other versions
DE69121047D1 (de
Inventor
Isahiro C/O Intellectual Prop. Div Minato-Ku Tokyo 105 Hasegawa
Yoshihisa 303 Sanno-Heights Yokohama-Shi Hirano
C/O Intellectual Prop. Div. Minato-Ku Tokyo 105 Horioka Keiji
Yoshifumi A202 Hachibanchi-Corpo Kanagawa-Ken Tahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Tokyo Electron Ltd
Original Assignee
Toshiba Corp
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Electron Ltd filed Critical Toshiba Corp
Publication of DE69121047D1 publication Critical patent/DE69121047D1/de
Application granted granted Critical
Publication of DE69121047T2 publication Critical patent/DE69121047T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
  • Static Random-Access Memory (AREA)
DE69121047T 1990-10-19 1991-10-18 Ätzverfahren für Materialien aus Oxid Expired - Lifetime DE69121047T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP28315590 1990-10-19
JP30036190 1990-11-05

Publications (2)

Publication Number Publication Date
DE69121047D1 DE69121047D1 (de) 1996-08-29
DE69121047T2 true DE69121047T2 (de) 1997-01-16

Family

ID=26554921

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69121047T Expired - Lifetime DE69121047T2 (de) 1990-10-19 1991-10-18 Ätzverfahren für Materialien aus Oxid

Country Status (6)

Country Link
US (1) US5302236A (enExample)
EP (1) EP0482519B1 (enExample)
JP (1) JP3390814B2 (enExample)
KR (2) KR910010516A (enExample)
DE (1) DE69121047T2 (enExample)
TW (1) TW219405B (enExample)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5880036A (en) * 1992-06-15 1999-03-09 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
JP2787646B2 (ja) 1992-11-27 1998-08-20 三菱電機株式会社 半導体装置の製造方法
DE4315435C2 (de) * 1993-05-08 1995-03-09 Itt Ind Gmbh Deutsche Verfahren zum selektiven Ätzen von auf einem Halbleitersubstrat angeordneten Isolier- und Pufferschichten
JP2720763B2 (ja) * 1993-09-17 1998-03-04 日本電気株式会社 半導体装置の製造方法
US5399237A (en) * 1994-01-27 1995-03-21 Applied Materials, Inc. Etching titanium nitride using carbon-fluoride and carbon-oxide gas
JPH08153708A (ja) * 1994-11-29 1996-06-11 Nec Corp エッチング装置およびエッチング方法
JP3778299B2 (ja) * 1995-02-07 2006-05-24 東京エレクトロン株式会社 プラズマエッチング方法
US5702567A (en) * 1995-06-01 1997-12-30 Kabushiki Kaisha Toshiba Plurality of photolithographic alignment marks with shape, size and spacing based on circuit pattern features
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
US5928967A (en) * 1996-06-10 1999-07-27 International Business Machines Corporation Selective oxide-to-nitride etch process using C4 F8 /CO/Ar
GB9616225D0 (en) 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
EP1357584A3 (en) * 1996-08-01 2005-01-12 Surface Technology Systems Plc Method of surface treatment of semiconductor substrates
KR19980064466A (ko) * 1996-12-23 1998-10-07 윌리엄비.켐플러 이산화탄소로 실리콘 산화물을 에칭하는 공정
US5882535A (en) * 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device
US6277720B1 (en) * 1997-06-30 2001-08-21 Texas Instruments Incorporated Silicon nitride dopant diffusion barrier in integrated circuits
KR100458085B1 (ko) * 1997-06-30 2005-02-23 주식회사 하이닉스반도체 반도체장치제조방법
US6187685B1 (en) 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
US5866485A (en) * 1997-09-29 1999-02-02 Siemens Aktiengesellschaft Techniques for etching a silicon dioxide-containing layer
US6054379A (en) 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6340435B1 (en) 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
JPH11354499A (ja) * 1998-04-07 1999-12-24 Oki Electric Ind Co Ltd コンタクトホール等の形成方法
US6455232B1 (en) 1998-04-14 2002-09-24 Applied Materials, Inc. Method of reducing stop layer loss in a photoresist stripping process using a fluorine scavenger
JP2991192B1 (ja) 1998-07-23 1999-12-20 日本電気株式会社 プラズマ処理方法及びプラズマ処理装置
US6417013B1 (en) 1999-01-29 2002-07-09 Plasma-Therm, Inc. Morphed processing of semiconductor devices
JP3241020B2 (ja) 1999-03-26 2001-12-25 日本電気株式会社 半導体装置の製造方法
US6255179B1 (en) 1999-08-04 2001-07-03 International Business Machines Corporation Plasma etch pre-silicide clean
US6500356B2 (en) * 2000-03-27 2002-12-31 Applied Materials, Inc. Selectively etching silicon using fluorine without plasma
US20030010354A1 (en) * 2000-03-27 2003-01-16 Applied Materials, Inc. Fluorine process for cleaning semiconductor process chamber
US6436841B1 (en) 2001-09-10 2002-08-20 Taiwan Semiconductor Manufacturing Company Selectivity oxide-to-oxynitride etch process using a fluorine containing gas, an inert gas and a weak oxidant
US7067439B2 (en) * 2002-06-14 2006-06-27 Applied Materials, Inc. ALD metal oxide deposition process using direct oxidation
JP4495471B2 (ja) * 2004-01-13 2010-07-07 三星電子株式会社 エッチング方法
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US20060105114A1 (en) * 2004-11-16 2006-05-18 White John M Multi-layer high quality gate dielectric for low-temperature poly-silicon TFTs
US7837838B2 (en) * 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7645710B2 (en) * 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7678710B2 (en) * 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US20080124937A1 (en) * 2006-08-16 2008-05-29 Songlin Xu Selective etching method and apparatus
WO2008039845A2 (en) * 2006-09-26 2008-04-03 Applied Materials, Inc. Fluorine plasma treatment of high-k gate stack for defect passivation
JP2010245101A (ja) * 2009-04-01 2010-10-28 Hitachi High-Technologies Corp ドライエッチング方法
JP6604911B2 (ja) * 2016-06-23 2019-11-13 東京エレクトロン株式会社 エッチング処理方法
EP3624171B1 (en) * 2017-06-08 2021-09-08 Showa Denko K.K. Etching method

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341076A (en) * 1976-09-27 1978-04-14 Toshiba Corp Process for treating bulb wastes containing mercury
JPS55143560A (en) * 1979-04-26 1980-11-08 Mitsubishi Electric Corp Manufacture of photomask
JPS56158452A (en) * 1980-05-12 1981-12-07 Mitsubishi Electric Corp Formation of pattern of electrode and wiring for semiconductor device
JPS57190320A (en) * 1981-05-20 1982-11-22 Toshiba Corp Dry etching method
JPS604270B2 (ja) * 1981-07-24 1985-02-02 三菱電機株式会社 クロム系膜のドライエツチング法
US4376672A (en) * 1981-10-26 1983-03-15 Applied Materials, Inc. Materials and methods for plasma etching of oxides and nitrides of silicon
JPS6077429A (ja) * 1983-10-04 1985-05-02 Asahi Glass Co Ltd ドライエツチング方法
JPH07105378B2 (ja) * 1984-08-24 1995-11-13 富士通株式会社 クロム系膜のドライエツチング方法
US4654112A (en) * 1984-09-26 1987-03-31 Texas Instruments Incorporated Oxide etch
US4582581A (en) * 1985-05-09 1986-04-15 Allied Corporation Boron trifluoride system for plasma etching of silicon dioxide
JPH0722152B2 (ja) * 1985-05-10 1995-03-08 ソニー株式会社 ドライエツチング方法
US4668338A (en) * 1985-12-30 1987-05-26 Applied Materials, Inc. Magnetron-enhanced plasma etching process
JPH0797575B2 (ja) * 1986-02-06 1995-10-18 沖電気工業株式会社 プラズマエツチング方法
US4786361A (en) * 1986-03-05 1988-11-22 Kabushiki Kaisha Toshiba Dry etching process
US4793897A (en) * 1987-03-20 1988-12-27 Applied Materials, Inc. Selective thin film etch process
US4844773A (en) * 1987-07-16 1989-07-04 Texas Instruments Incorporated Process for etching silicon nitride film
JPH0618182B2 (ja) * 1987-08-05 1994-03-09 松下電器産業株式会社 ドライエッチング装置
JP2640828B2 (ja) * 1988-06-28 1997-08-13 富士通株式会社 半導体基板表面の自然酸化膜の除去方法

Also Published As

Publication number Publication date
JPH05247673A (ja) 1993-09-24
DE69121047D1 (de) 1996-08-29
EP0482519A1 (en) 1992-04-29
KR100227772B1 (ko) 1999-11-01
KR920008866A (ko) 1992-05-28
EP0482519B1 (en) 1996-07-24
US5302236A (en) 1994-04-12
JP3390814B2 (ja) 2003-03-31
KR910010516A (ko) 1991-06-29
TW219405B (enExample) 1994-01-21

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