DE69322058T2 - Plasma-Ätzverfahren - Google Patents

Plasma-Ätzverfahren

Info

Publication number
DE69322058T2
DE69322058T2 DE69322058T DE69322058T DE69322058T2 DE 69322058 T2 DE69322058 T2 DE 69322058T2 DE 69322058 T DE69322058 T DE 69322058T DE 69322058 T DE69322058 T DE 69322058T DE 69322058 T2 DE69322058 T2 DE 69322058T2
Authority
DE
Germany
Prior art keywords
etching process
plasma etching
plasma
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69322058T
Other languages
English (en)
Other versions
DE69322058D1 (de
Inventor
Subhash Gupta
Susan H Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69322058D1 publication Critical patent/DE69322058D1/de
Application granted granted Critical
Publication of DE69322058T2 publication Critical patent/DE69322058T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69322058T 1992-10-09 1993-08-06 Plasma-Ätzverfahren Expired - Lifetime DE69322058T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/960,499 US5468339A (en) 1992-10-09 1992-10-09 Plasma etch process

Publications (2)

Publication Number Publication Date
DE69322058D1 DE69322058D1 (de) 1998-12-17
DE69322058T2 true DE69322058T2 (de) 1999-07-01

Family

ID=25503250

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322058T Expired - Lifetime DE69322058T2 (de) 1992-10-09 1993-08-06 Plasma-Ätzverfahren

Country Status (6)

Country Link
US (1) US5468339A (de)
EP (1) EP0596593B1 (de)
JP (1) JP3339920B2 (de)
KR (1) KR940010217A (de)
DE (1) DE69322058T2 (de)
TW (1) TW214606B (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468340A (en) * 1992-10-09 1995-11-21 Gupta; Subhash Highly selective high aspect ratio oxide etch method and products made by the process
US5935877A (en) * 1995-09-01 1999-08-10 Applied Materials, Inc. Etch process for forming contacts over titanium silicide
US5843846A (en) * 1996-12-31 1998-12-01 Intel Corporation Etch process to produce rounded top corners for sub-micron silicon trench applications
US5882535A (en) * 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device
US5961791A (en) * 1997-02-26 1999-10-05 Motorola, Inc. Process for fabricating a semiconductor device
US5893752A (en) * 1997-12-22 1999-04-13 Motorola, Inc. Process for forming a semiconductor device
US6090304A (en) * 1997-08-28 2000-07-18 Lam Research Corporation Methods for selective plasma etch
US6183655B1 (en) 1997-09-19 2001-02-06 Applied Materials, Inc. Tunable process for selectively etching oxide using fluoropropylene and a hydrofluorocarbon
US6066566A (en) * 1998-01-28 2000-05-23 International Business Machines Corporation High selectivity collar oxide etch processes
US6080676A (en) * 1998-09-17 2000-06-27 Advanced Micro Devices, Inc. Device and method for etching spacers formed upon an integrated circuit gate conductor
US6281132B1 (en) 1998-10-06 2001-08-28 Advanced Micro Devices, Inc. Device and method for etching nitride spacers formed upon an integrated circuit gate conductor
US6214742B1 (en) * 1998-12-07 2001-04-10 Advanced Micro Devices, Inc. Post-via tin removal for via resistance improvement
US6169036B1 (en) 1999-03-25 2001-01-02 Lucent Technologies Inc. Method for cleaning via openings in integrated circuit manufacturing
DE10027932C2 (de) * 2000-05-31 2003-10-02 Infineon Technologies Ag Verfahren zur Bildung eines Kontaktlochs in einer Isolierschicht eines elektronischen oder mikroelektronischen Bauelements
US6569774B1 (en) 2000-08-31 2003-05-27 Micron Technology, Inc. Method to eliminate striations and surface roughness caused by dry etch
US6630407B2 (en) * 2001-03-30 2003-10-07 Lam Research Corporation Plasma etching of organic antireflective coating
JP4176365B2 (ja) * 2002-03-25 2008-11-05 東京エレクトロン株式会社 プラズマエッチング方法
US7608195B2 (en) 2006-02-21 2009-10-27 Micron Technology, Inc. High aspect ratio contacts
US7648872B2 (en) * 2006-12-11 2010-01-19 Micron Technology, Inc. Methods of forming DRAM arrays

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028155A (en) * 1974-02-28 1977-06-07 Lfe Corporation Process and material for manufacturing thin film integrated circuits
JPS5813625B2 (ja) * 1979-12-12 1983-03-15 超エル・エス・アイ技術研究組合 ガスプラズマ食刻法
US4534816A (en) * 1984-06-22 1985-08-13 International Business Machines Corporation Single wafer plasma etch reactor
US5227335A (en) * 1986-11-10 1993-07-13 At&T Bell Laboratories Tungsten metallization
GB2214709A (en) * 1988-01-20 1989-09-06 Philips Nv A method of enabling connection to a substructure forming part of an electronic device
DD288481A5 (de) * 1989-10-12 1991-03-28 Veb Mikroelektronik "Anna Seghers" Neuhaus,De Verfahren zur plasmachemischen erzeugung von sio tief 2-strukturen fuer die herstellung von elektronischen bauelementen
US5254213A (en) * 1989-10-25 1993-10-19 Matsushita Electric Industrial Co., Ltd. Method of forming contact windows
US4978420A (en) * 1990-01-03 1990-12-18 Hewlett-Packard Company Single chamber via etch through a dual-layer dielectric
US5021121A (en) * 1990-02-16 1991-06-04 Applied Materials, Inc. Process for RIE etching silicon dioxide
US5213659A (en) * 1990-06-20 1993-05-25 Micron Technology, Inc. Combination usage of noble gases for dry etching semiconductor wafers
US5176790A (en) * 1991-09-25 1993-01-05 Applied Materials, Inc. Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal
US5269879A (en) * 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
US5284549A (en) * 1992-01-02 1994-02-08 International Business Machines Corporation Selective fluorocarbon-based RIE process utilizing a nitrogen additive
US5468340A (en) * 1992-10-09 1995-11-21 Gupta; Subhash Highly selective high aspect ratio oxide etch method and products made by the process

Also Published As

Publication number Publication date
JPH06151385A (ja) 1994-05-31
DE69322058D1 (de) 1998-12-17
EP0596593B1 (de) 1998-11-11
TW214606B (en) 1993-10-11
US5468339A (en) 1995-11-21
EP0596593A1 (de) 1994-05-11
JP3339920B2 (ja) 2002-10-28
KR940010217A (ko) 1994-05-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition