DE69113456T2 - Verfahren zur herstellung einer vielschichtleiterplatte. - Google Patents

Verfahren zur herstellung einer vielschichtleiterplatte.

Info

Publication number
DE69113456T2
DE69113456T2 DE69113456T DE69113456T DE69113456T2 DE 69113456 T2 DE69113456 T2 DE 69113456T2 DE 69113456 T DE69113456 T DE 69113456T DE 69113456 T DE69113456 T DE 69113456T DE 69113456 T2 DE69113456 T2 DE 69113456T2
Authority
DE
Germany
Prior art keywords
pct
layers
resin
metal
inner layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69113456T
Other languages
English (en)
Other versions
DE69113456D1 (de
Inventor
Jiri Masik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
POLYCLAD EUROP AB
Original Assignee
POLYCLAD EUROP AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by POLYCLAD EUROP AB filed Critical POLYCLAD EUROP AB
Application granted granted Critical
Publication of DE69113456D1 publication Critical patent/DE69113456D1/de
Publication of DE69113456T2 publication Critical patent/DE69113456T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0285—Using ultrasound, e.g. for cleaning, soldering or wet treatment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/065—Binding insulating layers without adhesive, e.g. by local heating or welding, before lamination of the whole PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/102—Using microwaves, e.g. for curing ink patterns or adhesive

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
DE69113456T 1990-05-16 1991-04-17 Verfahren zur herstellung einer vielschichtleiterplatte. Expired - Fee Related DE69113456T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9001766A SE465399B (sv) 1990-05-16 1990-05-16 Saett vid tillverkning av flerlagermoensterkort
PCT/SE1991/000270 WO1991018491A1 (en) 1990-05-16 1991-04-17 Process for the production of a multilayer printed circuit board

Publications (2)

Publication Number Publication Date
DE69113456D1 DE69113456D1 (de) 1995-11-02
DE69113456T2 true DE69113456T2 (de) 1996-04-04

Family

ID=20379505

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69113456T Expired - Fee Related DE69113456T2 (de) 1990-05-16 1991-04-17 Verfahren zur herstellung einer vielschichtleiterplatte.

Country Status (8)

Country Link
US (1) US5336353A (de)
EP (1) EP0528963B1 (de)
JP (1) JPH05507388A (de)
AT (1) ATE128598T1 (de)
AU (1) AU7970691A (de)
DE (1) DE69113456T2 (de)
SE (1) SE465399B (de)
WO (1) WO1991018491A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112533400A (zh) * 2019-09-19 2021-03-19 宏启胜精密电子(秦皇岛)有限公司 电路板的制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMC960043A1 (it) * 1996-04-05 1997-10-05 So Ma Ci S Spa Sistema per mantenere bloccati i pannelli dei circuiti stampati multistrato durante la polimerizzazione dei fogli isolanti intermedi
DE19958644A1 (de) * 1999-12-06 2001-10-04 Schweizer Electronic Ag Verfahren und Vorrichtung zur Herstellung von Multilayern
US6682802B2 (en) 2000-12-14 2004-01-27 Intel Corporation Selective PCB stiffening with preferentially oriented fibers
EP1220590A1 (de) * 2000-12-22 2002-07-03 TAPEMATIC S.p.A. Verfahren zur Herstellung von mehrschichtigen Karten für gedruckte Schaltungen
JP2005026608A (ja) * 2003-07-02 2005-01-27 Tokyo Electron Ltd 接合方法および接合装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2917472C2 (de) * 1979-04-30 1986-10-16 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Unverstiftet verpreßte Mehrlagenleiterplatte und Verfahren zu deren Herstellung
DE3240754A1 (de) * 1981-11-06 1983-05-19 Sumitomo Bakelite Co. Ltd., Tokyo Gedruckte schaltung mit mehreren schichten und verfahren zu deren herstellung
US4481533A (en) * 1981-11-27 1984-11-06 Lenkeit Industries, Inc. Method and apparatus for successively positioning sheets of material with precision for punching aligning holes in the sheets enabling the sheets to be used in the manufacture of composite circuit boards
DE3423181A1 (de) * 1984-06-22 1986-01-02 Dielektra GmbH, 5000 Köln Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten
US4702785A (en) * 1985-06-24 1987-10-27 President Engineering Corporation Process for manufacturing multilayer PC boards
JPS62233211A (ja) * 1986-04-02 1987-10-13 Matsushita Electric Works Ltd 積層板の製造方法
JPH072392B2 (ja) * 1986-07-18 1995-01-18 日立化成工業株式会社 積層板
JPH0728127B2 (ja) * 1986-08-28 1995-03-29 東芝ケミカル株式会社 多層回路積層板の製造方法
JPH0298195A (ja) * 1988-10-04 1990-04-10 Mitsubishi Electric Corp 多層プリント基板の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112533400A (zh) * 2019-09-19 2021-03-19 宏启胜精密电子(秦皇岛)有限公司 电路板的制造方法
CN112533400B (zh) * 2019-09-19 2022-04-15 宏启胜精密电子(秦皇岛)有限公司 电路板的制造方法

Also Published As

Publication number Publication date
US5336353A (en) 1994-08-09
SE9001766L (sv) 1991-09-02
WO1991018491A1 (en) 1991-11-28
EP0528963B1 (de) 1995-09-27
DE69113456D1 (de) 1995-11-02
JPH05507388A (ja) 1993-10-21
SE465399B (sv) 1991-09-02
ATE128598T1 (de) 1995-10-15
EP0528963A1 (de) 1993-03-03
SE9001766D0 (sv) 1990-05-16
AU7970691A (en) 1991-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee