DE69015494D1 - Selbstausrichtende Justiermarke für die Herstellung von integrierten Schaltungen. - Google Patents

Selbstausrichtende Justiermarke für die Herstellung von integrierten Schaltungen.

Info

Publication number
DE69015494D1
DE69015494D1 DE69015494T DE69015494T DE69015494D1 DE 69015494 D1 DE69015494 D1 DE 69015494D1 DE 69015494 T DE69015494 T DE 69015494T DE 69015494 T DE69015494 T DE 69015494T DE 69015494 D1 DE69015494 D1 DE 69015494D1
Authority
DE
Germany
Prior art keywords
self
production
integrated circuits
alignment mark
aligning alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015494T
Other languages
English (en)
Other versions
DE69015494T2 (de
Inventor
Robert Louis Kostelak
William Thomas Lynch
Sheila Vaidya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69015494D1 publication Critical patent/DE69015494D1/de
Application granted granted Critical
Publication of DE69015494T2 publication Critical patent/DE69015494T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Bipolar Transistors (AREA)
DE69015494T 1989-07-31 1990-07-20 Selbstausrichtende Justiermarke für die Herstellung von integrierten Schaltungen. Expired - Fee Related DE69015494T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/387,721 US4992394A (en) 1989-07-31 1989-07-31 Self aligned registration marks for integrated circuit fabrication

Publications (2)

Publication Number Publication Date
DE69015494D1 true DE69015494D1 (de) 1995-02-09
DE69015494T2 DE69015494T2 (de) 1995-05-04

Family

ID=23531108

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015494T Expired - Fee Related DE69015494T2 (de) 1989-07-31 1990-07-20 Selbstausrichtende Justiermarke für die Herstellung von integrierten Schaltungen.

Country Status (6)

Country Link
US (1) US4992394A (de)
EP (1) EP0411797B1 (de)
JP (1) JP2803734B2 (de)
DE (1) DE69015494T2 (de)
HK (1) HK49296A (de)
SG (1) SG31595G (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59009067D1 (de) * 1990-04-27 1995-06-14 Siemens Ag Verfahren zur Herstellung einer Öffnung in einem Halbleiterschichtaufbau und dessen Verwendung zur Herstellung von Kontaktlöchern.
US5162259A (en) * 1991-02-04 1992-11-10 Motorola, Inc. Method for forming a buried contact in a semiconductor device
IT1251393B (it) * 1991-09-04 1995-05-09 St Microelectronics Srl Procedimento per la realizzazione di strutture metrologiche particolarmente per l'analisi dell'accuratezza di strumenti di misura di allineamento su substrati processati.
JP3115107B2 (ja) * 1992-07-02 2000-12-04 株式会社東芝 レチクルとそのレチクルを用いた半導体装置およびその製造方法
KR960014963B1 (ko) * 1993-10-15 1996-10-23 현대전자산업 주식회사 반도체 장치의 제조 방법
US5650629A (en) * 1994-06-28 1997-07-22 The United States Of America As Represented By The Secretary Of The Air Force Field-symmetric beam detector for semiconductors
JPH0927529A (ja) * 1995-07-12 1997-01-28 Sony Corp 位置合わせ検出用半導体装置
DE19534784C1 (de) * 1995-09-19 1997-04-24 Siemens Ag Halbleiter-Schaltungselement und Verfahren zu seiner Herstellung
US5764366A (en) * 1995-11-30 1998-06-09 Lucent Technologies Inc. Method and apparatus for alignment and bonding
US5757503A (en) * 1995-12-26 1998-05-26 Lucent Technologies Inc. Method and apparatus for fabricating products using alignment measuring technique
US6307273B1 (en) * 1996-06-07 2001-10-23 Vanguard International Semiconductor Corporation High contrast, low noise alignment mark for laser trimming of redundant memory arrays
US5668065A (en) * 1996-08-01 1997-09-16 Winbond Electronics Corp. Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects
US5872042A (en) * 1996-08-22 1999-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for alignment mark regeneration
JP3519579B2 (ja) * 1997-09-09 2004-04-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US5863825A (en) * 1997-09-29 1999-01-26 Lsi Logic Corporation Alignment mark contrast enhancement
US6008060A (en) * 1998-04-14 1999-12-28 Etec Systems, Inc. Detecting registration marks with a low energy electron beam
US6120607A (en) * 1998-12-03 2000-09-19 Lsi Logic Corporation Apparatus and method for blocking the deposition of oxide on a wafer
US6146910A (en) * 1999-02-02 2000-11-14 The United States Of America, As Represented By The Secretary Of Commerce Target configuration and method for extraction of overlay vectors from targets having concealed features
DE19904571C1 (de) * 1999-02-04 2000-04-20 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung aus zwei Substraten, wobei die Schaltungsstrukturen des Substrate exakt gegeneinander ausgerichtet sind
US6294018B1 (en) * 1999-09-15 2001-09-25 Lucent Technologies Alignment techniques for epitaxial growth processes
US6423555B1 (en) 2000-08-07 2002-07-23 Advanced Micro Devices, Inc. System for determining overlay error
TWI288428B (en) * 2004-01-21 2007-10-11 Seiko Epson Corp Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment
KR100695876B1 (ko) * 2005-06-24 2007-03-19 삼성전자주식회사 오버레이 키 및 그 형성 방법, 오버레이 키를 이용하여형성된 반도체 장치 및 그 제조 방법.
JP2011040687A (ja) * 2009-08-18 2011-02-24 Sumitomo Electric Ind Ltd 半導体レーザの製造方法
CN102543733B (zh) * 2010-12-08 2016-03-02 无锡华润上华科技有限公司 Dmos工艺流程中的对位标记方法
GB201816838D0 (en) * 2018-10-16 2018-11-28 Smith & Nephew Systems and method for applying biocompatible encapsulation to sensor enabled wound monitoring and therapy dressings
CN110400752B (zh) * 2019-08-29 2020-06-16 武汉新芯集成电路制造有限公司 Ldmos器件及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1550867A (en) * 1975-08-04 1979-08-22 Hughes Aircraft Co Positioning method and apparatus for fabricating microcircuit devices
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
JPS5575229A (en) * 1978-12-01 1980-06-06 Mitsubishi Electric Corp Semiconductor device
JPS564229A (en) * 1979-06-26 1981-01-17 Toshiba Corp Semiconductor device
JPS5694741A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Positioning mark for electronic beam exposure
US4351892A (en) * 1981-05-04 1982-09-28 Fairchild Camera & Instrument Corp. Alignment target for electron-beam write system
US4407933A (en) * 1981-06-11 1983-10-04 Bell Telephone Laboratories, Incorporated Alignment marks for electron beam lithography
JPS5875838A (ja) * 1981-10-30 1983-05-07 Seiko Instr & Electronics Ltd シリコン基板の加工方法
JPS5972724A (ja) * 1982-10-20 1984-04-24 Hitachi Ltd 位置合せ方法
JPS60111424A (ja) * 1983-11-22 1985-06-17 Toshiba Corp 位置合わせ用マ−クの形成方法
JPS6143424A (ja) * 1984-08-08 1986-03-03 Hitachi Ltd 高精度の位置合せ方法
JPS61100928A (ja) * 1984-10-22 1986-05-19 Mitsubishi Electric Corp 半導体基板の位置合せマ−ク形成方法
JPS62211957A (ja) * 1986-03-13 1987-09-17 Fujitsu Ltd 電界効果トランジスタの製造方法
JPS62271427A (ja) * 1986-05-20 1987-11-25 Matsushita Electric Ind Co Ltd マスク位置合わせ方法

Also Published As

Publication number Publication date
SG31595G (en) 1995-08-18
HK49296A (en) 1996-03-29
EP0411797A1 (de) 1991-02-06
EP0411797B1 (de) 1994-12-28
JPH0366116A (ja) 1991-03-20
DE69015494T2 (de) 1995-05-04
US4992394A (en) 1991-02-12
JP2803734B2 (ja) 1998-09-24

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee