DE68922474D1 - Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten. - Google Patents

Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten.

Info

Publication number
DE68922474D1
DE68922474D1 DE68922474T DE68922474T DE68922474D1 DE 68922474 D1 DE68922474 D1 DE 68922474D1 DE 68922474 T DE68922474 T DE 68922474T DE 68922474 T DE68922474 T DE 68922474T DE 68922474 D1 DE68922474 D1 DE 68922474D1
Authority
DE
Germany
Prior art keywords
layers
making
make
connection
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68922474T
Other languages
English (en)
Other versions
DE68922474T2 (de
Inventor
Claudine Villalon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR8816230A external-priority patent/FR2640427A1/fr
Priority claimed from FR8912263A external-priority patent/FR2652201A1/fr
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of DE68922474D1 publication Critical patent/DE68922474D1/de
Application granted granted Critical
Publication of DE68922474T2 publication Critical patent/DE68922474T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)
DE68922474T 1988-12-09 1989-12-04 Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten. Expired - Fee Related DE68922474T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8816230A FR2640427A1 (fr) 1988-12-09 1988-12-09 Procede de realisation d'un circuit integre incluant des etapes pour realiser de maniere selective des ouvertures en surface de motifs realises a un dit premier niveau
FR8912263A FR2652201A1 (fr) 1989-09-19 1989-09-19 Procede de realisation d'un circuit integre incluant des etapes pour realiser des interconnexions entre des motifs realises a des niveaux differents.

Publications (2)

Publication Number Publication Date
DE68922474D1 true DE68922474D1 (de) 1995-06-08
DE68922474T2 DE68922474T2 (de) 1996-01-11

Family

ID=26227041

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68922474T Expired - Fee Related DE68922474T2 (de) 1988-12-09 1989-12-04 Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten.

Country Status (4)

Country Link
US (1) US5006485A (de)
EP (1) EP0372644B1 (de)
JP (1) JP2798452B2 (de)
DE (1) DE68922474T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182235A (en) * 1985-02-20 1993-01-26 Mitsubishi Denki Kabushiki Kaisha Manufacturing method for a semiconductor device having a bias sputtered insulating film
US5658425A (en) * 1991-10-16 1997-08-19 Lam Research Corporation Method of etching contact openings with reduced removal rate of underlying electrically conductive titanium silicide layer
US5269879A (en) * 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
KR940008372B1 (ko) * 1992-01-16 1994-09-12 삼성전자 주식회사 반도체 기판의 층간 절연막의 평탄화 방법
US5302551A (en) * 1992-05-11 1994-04-12 National Semiconductor Corporation Method for planarizing the surface of an integrated circuit over a metal interconnect layer
KR950006343B1 (ko) * 1992-05-16 1995-06-14 금성일렉트론주식회사 반도체 장치의 제조방법
TW243544B (de) * 1992-12-31 1995-03-21 At & T Corp
US5286675A (en) * 1993-04-14 1994-02-15 Industrial Technology Research Institute Blanket tungsten etchback process using disposable spin-on-glass
US5723380A (en) * 1996-03-25 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of approach to improve metal lithography and via-plug integration
KR100190048B1 (ko) * 1996-06-25 1999-06-01 윤종용 반도체 소자의 소자 분리 방법
US5916453A (en) 1996-09-20 1999-06-29 Fujitsu Limited Methods of planarizing structures on wafers and substrates by polishing
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4349609A (en) * 1979-06-21 1982-09-14 Fujitsu Limited Electronic device having multilayer wiring structure
JPS5919354A (ja) * 1982-07-24 1984-01-31 Fujitsu Ltd 半導体装置
FR2537779B1 (fr) * 1982-12-10 1986-03-14 Commissariat Energie Atomique Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
US4541169A (en) * 1984-10-29 1985-09-17 International Business Machines Corporation Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip
DE3443793A1 (de) * 1984-11-30 1986-06-12 Siemens AG, 1000 Berlin und 8000 München Verfahren zum kontaktieren von halbleiterbauelementen
US4671849A (en) * 1985-05-06 1987-06-09 International Business Machines Corporation Method for control of etch profile
US4666553A (en) * 1985-08-28 1987-05-19 Rca Corporation Method for planarizing multilayer semiconductor devices
FR2587838B1 (fr) * 1985-09-20 1987-11-27 Radiotechnique Compelec Procede pour aplanir la surface d'un dispositif semi-conducteur utilisant du nitrure de silicium comme materiau isolant
US4676868A (en) * 1986-04-23 1987-06-30 Fairchild Semiconductor Corporation Method for planarizing semiconductor substrates
US4839311A (en) * 1987-08-14 1989-06-13 National Semiconductor Corporation Etch back detection

Also Published As

Publication number Publication date
DE68922474T2 (de) 1996-01-11
US5006485A (en) 1991-04-09
JP2798452B2 (ja) 1998-09-17
EP0372644B1 (de) 1995-05-03
JPH02192730A (ja) 1990-07-30
EP0372644A1 (de) 1990-06-13

Similar Documents

Publication Publication Date Title
DE3483280D1 (de) Verfahren zum herstellen einer mehrschicht-halbleiteranordnung.
DE68911621D1 (de) Verfahren zum Herstellen einer Einrichtung.
DE3584757D1 (de) Verfahren zum herstellen einer zwei-wannen-cmos-halbleiterstruktur.
DE3586732D1 (de) Verfahren zum herstellen einer dreidimentionaler halbleiteranordung.
DE3583934D1 (de) Verfahren zum herstellen einer halbleiterverbundanordnung.
DE69023524D1 (de) Verfahren zum Herstellen einer Multischichtenverbindungsstruktur.
DE69126934D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung mit Mehrlagen-Verbindungsleitungen
DE3483579D1 (de) Verfahren zum herstellen einer leiterbahn.
DE68917995D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE3686600D1 (de) Verfahren zum herstellen einer harzumhuellten halbleiteranordnung.
DE68919549D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE3686453D1 (de) Verfahren zum herstellen einer duennen halbleiterschicht.
DE3585180D1 (de) Verfahren zum herstellen einer halbleiteranordnung mit leiterschichten.
DE3780369D1 (de) Verfahren zum herstellen einer halbleiterstruktur.
DE3786914D1 (de) Verfahren zum herstellen einer integrierten schaltungspackungsstruktur.
DE68926224D1 (de) Verfahren zum Herstellen einer BICMOS-Anordnung
DE3586109D1 (de) Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung.
DE3483531D1 (de) Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet.
DE3671580D1 (de) Verfahren zum herstellen eines mehrschicht-keramiksubstrats.
DE3881794D1 (de) Verfahren zum herstellen eines mehrschichtigen geformten gegenstandes.
DE3772900D1 (de) Verfahren zum herstellen einer duennschichtschaltung und nach diesem verfahren hergestellte passive schaltung.
DE68920094D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68922474D1 (de) Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten.
DE3667361D1 (de) Verfahren zum herstellen eines metallischen verbindungsmusters fuer hochintegrierte schaltungsbauelemente.
DE68918306D1 (de) Verfahren zum Herstellen einer integrierten optoelektronischen Schaltung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee