DE68921086T2 - Integrierte Halbleiterschaltkreisanordnung mit verbesserter Eingangs-/ Ausgangsschnittstellenschaltung. - Google Patents

Integrierte Halbleiterschaltkreisanordnung mit verbesserter Eingangs-/ Ausgangsschnittstellenschaltung.

Info

Publication number
DE68921086T2
DE68921086T2 DE68921086T DE68921086T DE68921086T2 DE 68921086 T2 DE68921086 T2 DE 68921086T2 DE 68921086 T DE68921086 T DE 68921086T DE 68921086 T DE68921086 T DE 68921086T DE 68921086 T2 DE68921086 T2 DE 68921086T2
Authority
DE
Germany
Prior art keywords
circuit
input
output
output interface
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68921086T
Other languages
English (en)
Other versions
DE68921086D1 (de
Inventor
Shoji Matsushita
Masaharu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE68921086D1 publication Critical patent/DE68921086D1/de
Application granted granted Critical
Publication of DE68921086T2 publication Critical patent/DE68921086T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE68921086T 1988-04-08 1989-04-07 Integrierte Halbleiterschaltkreisanordnung mit verbesserter Eingangs-/ Ausgangsschnittstellenschaltung. Expired - Fee Related DE68921086T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63086871A JPH01259274A (ja) 1988-04-08 1988-04-08 集積回路の試験方式

Publications (2)

Publication Number Publication Date
DE68921086D1 DE68921086D1 (de) 1995-03-23
DE68921086T2 true DE68921086T2 (de) 1995-10-12

Family

ID=13898887

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68921086T Expired - Fee Related DE68921086T2 (de) 1988-04-08 1989-04-07 Integrierte Halbleiterschaltkreisanordnung mit verbesserter Eingangs-/ Ausgangsschnittstellenschaltung.

Country Status (5)

Country Link
US (1) US4970410A (de)
EP (1) EP0336444B1 (de)
JP (1) JPH01259274A (de)
KR (1) KR930000894B1 (de)
DE (1) DE68921086T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2566005B2 (ja) * 1989-03-03 1996-12-25 株式会社東芝 入力切換装置
FR2660071B1 (fr) * 1990-03-23 1992-07-24 Alcatel Radiotelephone Systeme de test d'un circuit imprime pourvu de circuits integres et application de ce systeme au test d'un tel circuit imprime.
US5079442A (en) * 1990-03-28 1992-01-07 Advanced Micro Devices, Inc. Apparatus adaptable for use as a replacement output driver in a signal generating circuit
US5498976A (en) * 1990-10-26 1996-03-12 Acer Incorporated Parallel buffer/driver configuration between data sending terminal and data receiving terminal
JP2563679B2 (ja) * 1991-01-24 1996-12-11 シャープ株式会社 双方向入出力信号分離回路
US5159278A (en) * 1991-04-02 1992-10-27 Vlsi Technology, Inc. State machine architecture providing increased resolution of output timing
GB9111179D0 (en) * 1991-05-23 1991-07-17 Motorola Gmbh An implementation of the ieee 1149.1 boundary-scan architecture
US5369645A (en) * 1991-07-02 1994-11-29 Hewlett-Packard Company Testing integrated circuit pad input and output structures
US5182467A (en) * 1991-08-22 1993-01-26 Triquint Semiconductor, Inc. High performance multiplexer for improving bit error rate
US5436575A (en) * 1991-09-03 1995-07-25 Altera Corporation Programmable logic array integrated circuits
US5883850A (en) * 1991-09-03 1999-03-16 Altera Corporation Programmable logic array integrated circuits
US5311081A (en) * 1992-04-01 1994-05-10 Digital Equipment Corporation Data bus using open drain drivers and differential receivers together with distributed termination impedances
JPH0756660A (ja) * 1993-08-13 1995-03-03 Fujitsu Ltd バス回路における消費電力削減制御方法および回路
JP2671817B2 (ja) * 1994-08-26 1997-11-05 日本電気株式会社 半導体集積回路の検査方法
US5970255A (en) 1995-10-16 1999-10-19 Altera Corporation System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly
US6058443A (en) * 1997-02-18 2000-05-02 Advanced Micro Devices, Inc. System for partitioning PC chipset functions into logic and port integrated circuits
US6271679B1 (en) 1999-03-24 2001-08-07 Altera Corporation I/O cell configuration for multiple I/O standards
US6836151B1 (en) * 1999-03-24 2004-12-28 Altera Corporation I/O cell configuration for multiple I/O standards
EP1139220B1 (de) * 2000-03-02 2017-10-25 Texas Instruments Incorporated Erhaltung und Abgabe von Prozessoreingebauten Ablaufverfolgungs- und Taktinformationen
DE10353585B4 (de) * 2003-11-17 2005-09-15 Infineon Technologies Ag Unidirektionale Eingangsschaltanordnung, Halbleiterschaltung und Verfahren zur Prüfung einer Laufzeitverzögerung eines Eingangstreibers einer Halbleiterschaltung
DE10353586A1 (de) * 2003-11-17 2005-06-30 Infineon Technologies Ag Ein/Ausgangschaltanordnung für Halbleiterschaltungen und Verfahren zur Prüfung von Treiberschaltkreisen von Halbleiterschaltungen
WO2013088173A1 (en) 2011-12-14 2013-06-20 Wolfson Microelectronics Plc Data transfer
US9341672B2 (en) * 2013-03-12 2016-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for interconnect test
US9500700B1 (en) * 2013-11-15 2016-11-22 Xilinx, Inc. Circuits for and methods of testing the operation of an input/output port
CN114859218B (zh) * 2022-03-16 2023-06-23 厦门智多晶科技有限公司 一种fpga芯片中查找表的检测电路及检测方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124899A (en) * 1977-05-23 1978-11-07 Monolithic Memories, Inc. Programmable array logic circuit
JPS60192276A (ja) * 1984-03-13 1985-09-30 Toshiba Corp 論理ｌｓｉのテスト方式
US4684830A (en) * 1985-03-22 1987-08-04 Monolithic Memories, Inc. Output circuit for a programmable logic array
US4691161A (en) * 1985-06-13 1987-09-01 Raytheon Company Configurable logic gate array
US4763020B1 (en) * 1985-09-06 1997-07-08 Ricoh Kk Programmable logic device having plural programmable function cells
US4703484A (en) * 1985-12-19 1987-10-27 Harris Corporation Programmable integrated circuit fault detection apparatus
US4789951A (en) * 1986-05-16 1988-12-06 Advanced Micro Devices, Inc. Programmable array logic cell
EP0253914A1 (de) * 1986-07-23 1988-01-27 Deutsche ITT Industries GmbH Isolierschicht-Feldeffekttransistor-Gegentakttreiberstufe mit Kompensierung von Betriebsparameterschwankungen und Fertigungsstreuungen

Also Published As

Publication number Publication date
DE68921086D1 (de) 1995-03-23
EP0336444A2 (de) 1989-10-11
EP0336444A3 (de) 1991-01-30
KR930000894B1 (en) 1993-02-11
JPH01259274A (ja) 1989-10-16
KR890016391A (ko) 1989-11-29
EP0336444B1 (de) 1995-02-15
US4970410A (en) 1990-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee