GB893624A - A parallel-to-series converter for electronic computers - Google Patents

Abstract

893,624. Transistor bi-stable circuits. LICENTIA PATENT - VERWALTUNGS - G.m.b.H. July 27, 1960 [Aug. 4, 1959], No. 26128/60. Class 40(6). [Also in Group XIX] A shift register 10, used for the serial conversion of parallel outputs of a decoder 11, comprises a series of stores S o to S 3 which each receive an output of the decoder and which are rendered effective to store the output only on reception of a control pulse (t 2 ), the outputs of the stores S providing inputs to stores ZS u to ZS 2 of similar construction and controlled by a pulse t 3 following t 2 the output of each store ZS except the last being an input to the store S next higher in the series. Each store S or ZS is preferably constructed as in Fig. 2, NPN transistors II and IV forming a flip-flop the state of which is exhibited by the potential at the terminal B. If a control pulse is not present at terminal t (0 volts), transistor I is not conductive, diode DI/III is conductive, as is transistor III, and diode DIII/IV is blocked, with the result that the flip-flop II/IV is unaffected by input pulses at e or z. A control pulse at terminal t (12 volts) sends transistors I and II conductive, breaking the feedback between transistors II and IV and blocking diodes DII/IV and DI/III. The condition of transistor III, and thus transistor IV, is dependent on the input signal at e or z. Because of the double phasereversal at transistors III and IV the output signal is in phase with the input.