DE69031112D1 - CMOS-Taktgeberanordnung - Google Patents

CMOS-Taktgeberanordnung

Info

Publication number
DE69031112D1
DE69031112D1 DE69031112T DE69031112T DE69031112D1 DE 69031112 D1 DE69031112 D1 DE 69031112D1 DE 69031112 T DE69031112 T DE 69031112T DE 69031112 T DE69031112 T DE 69031112T DE 69031112 D1 DE69031112 D1 DE 69031112D1
Authority
DE
Germany
Prior art keywords
clock signal
input
generating
cmos
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69031112T
Other languages
English (en)
Inventor
Donald M Walters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69031112D1 publication Critical patent/DE69031112D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15006—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two programmable outputs

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)
DE69031112T 1989-12-04 1990-11-12 CMOS-Taktgeberanordnung Expired - Lifetime DE69031112D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/445,245 US5041738A (en) 1989-12-04 1989-12-04 CMOS clock generator having an adjustable overlap voltage

Publications (1)

Publication Number Publication Date
DE69031112D1 true DE69031112D1 (de) 1997-09-04

Family

ID=23768143

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031112T Expired - Lifetime DE69031112D1 (de) 1989-12-04 1990-11-12 CMOS-Taktgeberanordnung

Country Status (5)

Country Link
US (1) US5041738A (de)
EP (1) EP0431761B1 (de)
JP (1) JP3041385B2 (de)
AT (1) ATE155943T1 (de)
DE (1) DE69031112D1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204559A (en) * 1991-01-23 1993-04-20 Vitesse Semiconductor Corporation Method and apparatus for controlling clock skew
US5130566A (en) * 1991-07-29 1992-07-14 Fujitsu Limited Pulse generator circuit for producing simultaneous complementary output pulses
US5270580A (en) * 1991-07-29 1993-12-14 Fujitsu Limited Pulse generator circuit for producing simultaneous complementary output pulses
US5444405A (en) * 1992-03-02 1995-08-22 Seiko Epson Corporation Clock generator with programmable non-overlapping clock edge capability
US5491432A (en) * 1992-08-07 1996-02-13 Lsi Logic Corporation CMOS Differential driver circuit for high offset ground
US5345195A (en) * 1992-10-22 1994-09-06 United Memories, Inc. Low power Vcc and temperature independent oscillator
KR0135735B1 (ko) * 1992-11-04 1998-05-15 기다오까 다까시 소음발생을 억제하는 개량된 출력 드라이버 회로 및 번인테스트를 위한 개량된 반도체 집적회로 장치
US5389831A (en) * 1992-12-17 1995-02-14 Vlsi Technology, Inc. Clock generator for providing a pair of nonoverlapping clock signals with adjustable skew
JPH0738408A (ja) * 1993-07-19 1995-02-07 Sharp Corp バッファ回路
US5424661A (en) * 1993-08-12 1995-06-13 Winbond Electronics North America Corp. Sensor circuit
JP3441780B2 (ja) * 1994-02-21 2003-09-02 日本テキサス・インスツルメンツ株式会社 クロック信号生成回路
DE19548629C1 (de) * 1995-12-23 1997-07-24 Itt Ind Gmbh Deutsche Komplementäres Taktsystem
WO1997042707A1 (de) * 1996-05-06 1997-11-13 Siemens Aktiengesellschaft Taktsignalgenerator
US6381704B1 (en) 1998-01-29 2002-04-30 Texas Instruments Incorporated Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor
US6172522B1 (en) * 1998-08-13 2001-01-09 International Business Machines Corporation Slew rate controlled predriver circuit
US6163169A (en) * 1998-08-13 2000-12-19 International Business Machines Corporation CMOS tri-state control circuit for a bidirectional I/O with slew rate control
JP3789241B2 (ja) * 1998-12-01 2006-06-21 Ｎｅｃエレクトロニクス株式会社 バイアス回路及び半導体記憶装置
JP3478996B2 (ja) * 1999-06-01 2003-12-15 Ｎｅｃエレクトロニクス株式会社 低振幅ドライバ回路及びこれを含む半導体装置
JP2002026265A (ja) * 2000-07-06 2002-01-25 Toshiba Lsi System Support Kk 半導体集積回路およびその配置設計方法
US6459318B1 (en) * 2001-03-22 2002-10-01 Hewlett-Packard Company Programmable delay clock gaters
US6424190B1 (en) * 2001-09-13 2002-07-23 Broadcom Corporation Apparatus and method for delay matching of full and divided clock signals
US6774683B2 (en) * 2002-08-13 2004-08-10 Analog Devices, Inc. Control loop for minimal tailnode excursion of differential switches
JP2004320231A (ja) * 2003-04-14 2004-11-11 Renesas Technology Corp 半導体装置の出力回路
KR100596977B1 (ko) * 2004-08-20 2006-07-05 삼성전자주식회사 외부 기준 전압과 내부 기준 전압을 동시에 이용하는 기준전압 발생 회로 및 이를 이용한 기준 전압 발생 방법
KR101456207B1 (ko) * 2013-08-05 2014-11-03 숭실대학교산학협력단 스위칭 커패시터를 이용한 슬루 레이트 조절 장치
TWI658697B (zh) * 2018-08-02 2019-05-01 崛智科技有限公司 資料閂鎖電路及其脈波信號產生器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2030807B (en) * 1978-10-02 1982-11-10 Ibm Latch circuit
JPS62188096A (ja) * 1986-02-13 1987-08-17 Toshiba Corp 半導体記憶装置のリフレツシユ動作タイミング制御回路
JPS63136815A (ja) * 1986-11-28 1988-06-09 Mitsubishi Electric Corp 周期信号発生回路
US4855617A (en) * 1986-12-19 1989-08-08 Texas Instruments Incorporated Schottky transistor logic floating latch flip-flop
US4950920A (en) * 1987-09-30 1990-08-21 Kabushiki Kaisha Toshiba Complementary signal output circuit with reduced skew

Also Published As

Publication number Publication date
JPH03190416A (ja) 1991-08-20
EP0431761A3 (en) 1992-01-22
EP0431761B1 (de) 1997-07-23
ATE155943T1 (de) 1997-08-15
EP0431761A2 (de) 1991-06-12
US5041738A (en) 1991-08-20
JP3041385B2 (ja) 2000-05-15

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Legal Events

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8332 No legal effect for de