DE69936277D1 - Synchron-Halbleiterspeichervorrichtung - Google Patents
Synchron-HalbleiterspeichervorrichtungInfo
- Publication number
- DE69936277D1 DE69936277D1 DE69936277T DE69936277T DE69936277D1 DE 69936277 D1 DE69936277 D1 DE 69936277D1 DE 69936277 T DE69936277 T DE 69936277T DE 69936277 T DE69936277 T DE 69936277T DE 69936277 D1 DE69936277 D1 DE 69936277D1
- Authority
- DE
- Germany
- Prior art keywords
- iclk
- mode
- signal
- synchronous
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11740298 | 1998-04-27 | ||
JP11740298A JP3169071B2 (ja) | 1998-04-27 | 1998-04-27 | 同期型半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69936277D1 true DE69936277D1 (de) | 2007-07-26 |
DE69936277T2 DE69936277T2 (de) | 2007-10-04 |
Family
ID=14710770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69936277T Expired - Lifetime DE69936277T2 (de) | 1998-04-27 | 1999-04-26 | Synchron-Halbleiterspeichervorrichtung |
Country Status (7)
Country | Link |
---|---|
US (1) | US6175534B1 (de) |
EP (1) | EP0953987B1 (de) |
JP (1) | JP3169071B2 (de) |
KR (1) | KR100327858B1 (de) |
CN (1) | CN1143320C (de) |
DE (1) | DE69936277T2 (de) |
TW (1) | TW422979B (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4712183B2 (ja) * | 2000-11-30 | 2011-06-29 | 富士通セミコンダクター株式会社 | 同期型半導体装置、及び試験システム |
KR100400309B1 (ko) * | 2001-05-04 | 2003-10-01 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 내부 동작명령 발생장치 및 방법 |
KR100401506B1 (ko) * | 2001-05-10 | 2003-10-17 | 주식회사 하이닉스반도체 | 비동기 프리차지 기능을 갖는 싱크로노스 메모리 디바이스 |
US6782467B1 (en) | 2001-06-29 | 2004-08-24 | Cypress Semiconductor Corp. | Method and apparatus for fast limited core area access and cross-port word size multiplication in synchronous multiport memories |
KR100428684B1 (ko) * | 2001-09-24 | 2004-04-30 | 주식회사 하이닉스반도체 | 제어신호의 마스킹을 고려한 반도체 기억장치 |
JP3792602B2 (ja) | 2002-05-29 | 2006-07-05 | エルピーダメモリ株式会社 | 半導体記憶装置 |
KR100452335B1 (ko) * | 2002-11-25 | 2004-10-12 | 삼성전자주식회사 | 고속동작 테스트가 가능한 반도체 메모리장치의 데이터확장회로 및 그 방법 |
US7796464B1 (en) | 2003-06-27 | 2010-09-14 | Cypress Semiconductor Corporation | Synchronous memory with a shadow-cycle counter |
KR100505706B1 (ko) * | 2003-08-25 | 2005-08-02 | 삼성전자주식회사 | 테스트 패턴 신호의 주파수를 선택적으로 가변시키는반도체 메모리 장치의 테스트 장치 및 그 테스트 방법 |
DE102004030053B3 (de) * | 2004-06-22 | 2005-12-29 | Infineon Technologies Ag | Halbleiterspeichervorrichtung |
KR100812600B1 (ko) * | 2005-09-29 | 2008-03-13 | 주식회사 하이닉스반도체 | 주파수가 다른 복수의 클럭을 사용하는 반도체메모리소자 |
JP2012203970A (ja) * | 2011-03-28 | 2012-10-22 | Elpida Memory Inc | 半導体装置及び半導体装置の制御方法 |
KR20190075202A (ko) * | 2017-12-21 | 2019-07-01 | 에스케이하이닉스 주식회사 | 테스트 제어 회로, 이를 이용하는 반도체 메모리 장치 및 반도체 시스템 |
CN116844600B (zh) * | 2022-03-23 | 2024-05-03 | 长鑫存储技术有限公司 | 一种信号采样电路以及半导体存储器 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3346827B2 (ja) * | 1993-05-25 | 2002-11-18 | 三菱電機株式会社 | 同期型半導体記憶装置 |
US5384737A (en) * | 1994-03-08 | 1995-01-24 | Motorola Inc. | Pipelined memory having synchronous and asynchronous operating modes |
US5570381A (en) * | 1995-04-28 | 1996-10-29 | Mosaid Technologies Incorporated | Synchronous DRAM tester |
JP3710845B2 (ja) * | 1995-06-21 | 2005-10-26 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JP4141520B2 (ja) * | 1997-11-14 | 2008-08-27 | 株式会社ルネサステクノロジ | 同期型半導体記憶装置 |
-
1998
- 1998-04-27 JP JP11740298A patent/JP3169071B2/ja not_active Expired - Fee Related
-
1999
- 1999-04-26 US US09/299,839 patent/US6175534B1/en not_active Expired - Lifetime
- 1999-04-26 EP EP99107422A patent/EP0953987B1/de not_active Expired - Lifetime
- 1999-04-26 DE DE69936277T patent/DE69936277T2/de not_active Expired - Lifetime
- 1999-04-26 CN CNB991061020A patent/CN1143320C/zh not_active Expired - Fee Related
- 1999-04-27 KR KR1019990014992A patent/KR100327858B1/ko not_active IP Right Cessation
- 1999-04-27 TW TW088106802A patent/TW422979B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0953987A2 (de) | 1999-11-03 |
US6175534B1 (en) | 2001-01-16 |
CN1235352A (zh) | 1999-11-17 |
EP0953987B1 (de) | 2007-06-13 |
KR100327858B1 (ko) | 2002-03-09 |
EP0953987A3 (de) | 2005-06-08 |
DE69936277T2 (de) | 2007-10-04 |
CN1143320C (zh) | 2004-03-24 |
JP3169071B2 (ja) | 2001-05-21 |
JPH11312397A (ja) | 1999-11-09 |
KR19990083513A (ko) | 1999-11-25 |
TW422979B (en) | 2001-02-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |