SE9003888D0 - Sam data accessing circuit involving low operating current, and method thereof - Google Patents

Sam data accessing circuit involving low operating current, and method thereof

Info

Publication number
SE9003888D0
SE9003888D0 SE9003888A SE9003888A SE9003888D0 SE 9003888 D0 SE9003888 D0 SE 9003888D0 SE 9003888 A SE9003888 A SE 9003888A SE 9003888 A SE9003888 A SE 9003888A SE 9003888 D0 SE9003888 D0 SE 9003888D0
Authority
SE
Sweden
Prior art keywords
data
operating current
accessing circuit
clock signal
buffer
Prior art date
Application number
SE9003888A
Other languages
English (en)
Inventor
S Seo
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SE9003888D0 publication Critical patent/SE9003888D0/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Static Random-Access Memory (AREA)
SE9003888A 1990-07-09 1990-12-06 Sam data accessing circuit involving low operating current, and method thereof SE9003888D0 (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900010364A KR920004417B1 (ko) 1990-07-09 1990-07-09 낮은 동작 전류를 갖는 sam 데이터 억세스회로 및 그 방법

Publications (1)

Publication Number Publication Date
SE9003888D0 true SE9003888D0 (sv) 1990-12-06

Family

ID=19301060

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9003888A SE9003888D0 (sv) 1990-07-09 1990-12-06 Sam data accessing circuit involving low operating current, and method thereof

Country Status (10)

Country Link
US (1) US5119333A (sv)
JP (1) JPH06103596B2 (sv)
KR (1) KR920004417B1 (sv)
CN (1) CN1022958C (sv)
DE (1) DE4040054A1 (sv)
FR (1) FR2664422B1 (sv)
GB (1) GB2246004B (sv)
HK (1) HK80095A (sv)
IT (1) IT1242185B (sv)
SE (1) SE9003888D0 (sv)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2719852B2 (ja) * 1991-03-07 1998-02-25 三菱電機株式会社 半導体記憶装置およびそれからのデータ読出方法
JPH0963262A (ja) * 1995-08-17 1997-03-07 Fujitsu Ltd シンクロナスｄｒａｍ
KR0167687B1 (ko) * 1995-09-11 1999-02-01 김광호 고속액세스를 위한 데이타 출력패스를 구비하는 반도체 메모리장치
JPH09180435A (ja) * 1995-12-28 1997-07-11 Mitsubishi Electric Corp 半導体記憶装置
GB2355097B (en) * 1996-08-13 2001-05-23 Fujitsu Ltd Semiconductor device
TW340262B (en) 1996-08-13 1998-09-11 Fujitsu Ltd Semiconductor device, system consisting of semiconductor devices and digital delay circuit
KR100335397B1 (ko) * 1998-05-25 2002-09-05 주식회사 하이닉스반도체 센스앰프순차구동장치
KR100301046B1 (ko) * 1998-09-01 2001-09-06 윤종용 그래픽처리속도를향상시킬수있는듀얼포트를갖는고속싱크로너스메모리장치
EP2105750B1 (de) * 2008-03-28 2011-01-19 Micronas GmbH Schaltungsanordnung, Vorrichtung bzw. Verfahren zum seriellen Senden von Daten über einen Anschlusskontakt
KR101647333B1 (ko) 2016-04-20 2016-08-10 창원대학교 산학협력단 롱피치형 롤러체인 어셈블리의 마모시험장치
KR101631693B1 (ko) 2016-04-22 2016-06-20 창원대학교 산학협력단 롱피치형 롤러체인 어셈블리용 마모시험장치
FR3066033B1 (fr) * 2017-05-05 2019-06-21 Stmicroelectronics (Rousset) Sas Dispositif d'etage tampon, en particulier apte a etre connecte sur un bus du type interface de peripherique serie

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649516A (en) * 1984-06-01 1987-03-10 International Business Machines Corp. Dynamic row buffer circuit for DRAM
DE3435752A1 (de) * 1984-09-28 1986-04-10 Siemens AG, 1000 Berlin und 8000 München Schaltung zur zwischenspeicherung digitaler signale
JPS62226498A (ja) * 1986-03-28 1987-10-05 Hitachi Ltd 半導体記憶装置
JP2591010B2 (ja) * 1988-01-29 1997-03-19 日本電気株式会社 シリアルアクセスメモリ装置
JPH0713858B2 (ja) * 1988-08-30 1995-02-15 三菱電機株式会社 半導体記憶装置
JPH07111829B2 (ja) * 1988-09-12 1995-11-29 株式会社東芝 半導体メモリ

Also Published As

Publication number Publication date
IT9048595A0 (it) 1990-12-18
KR920003169A (ko) 1992-02-29
JPH06103596B2 (ja) 1994-12-14
KR920004417B1 (ko) 1992-06-04
GB2246004A (en) 1992-01-15
US5119333A (en) 1992-06-02
FR2664422A1 (fr) 1992-01-10
DE4040054A1 (de) 1992-01-23
IT9048595A1 (it) 1992-01-10
GB9027075D0 (en) 1991-02-06
GB2246004B (en) 1994-08-17
HK80095A (en) 1995-06-01
FR2664422B1 (fr) 1993-11-19
DE4040054C2 (sv) 1993-06-03
CN1058115A (zh) 1992-01-22
IT1242185B (it) 1994-02-16
JPH04229483A (ja) 1992-08-18
CN1022958C (zh) 1993-12-01

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