JPS6425621A - High impedance preventing circuit - Google Patents

High impedance preventing circuit

Info

Publication number
JPS6425621A
JPS6425621A JP62183863A JP18386387A JPS6425621A JP S6425621 A JPS6425621 A JP S6425621A JP 62183863 A JP62183863 A JP 62183863A JP 18386387 A JP18386387 A JP 18386387A JP S6425621 A JPS6425621 A JP S6425621A
Authority
JP
Japan
Prior art keywords
level
circuit
buffer circuit
inverter buffer
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183863A
Other languages
Japanese (ja)
Inventor
Hisashi Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62183863A priority Critical patent/JPS6425621A/en
Publication of JPS6425621A publication Critical patent/JPS6425621A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To improve the flexibility by holding an input signal level of an inverter buffer circuit just before when an output impedance of a tri-state buffer is high so as to give the level to the input terminal of the titled circuit. CONSTITUTION:When the output impedance of the tri-state buffers 1-4 is all high independently of the number, an input level hold circuit 9 holds the input signal level of the inverter buffer circuit 10 just before and gives it to the input terminal of the inverter buffer circuit 10 thereby keeping the input level of the inverter buffer circuit 10 to a low or a high level. Then either of P, N-channel TRs 7, 8 of the inverter buffer circuit 10 is turned on. Thus, it is prevented that the drive impedance to a logic integrated circuit 12 is a high impedance.
JP62183863A 1987-07-22 1987-07-22 High impedance preventing circuit Pending JPS6425621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183863A JPS6425621A (en) 1987-07-22 1987-07-22 High impedance preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183863A JPS6425621A (en) 1987-07-22 1987-07-22 High impedance preventing circuit

Publications (1)

Publication Number Publication Date
JPS6425621A true JPS6425621A (en) 1989-01-27

Family

ID=16143143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183863A Pending JPS6425621A (en) 1987-07-22 1987-07-22 High impedance preventing circuit

Country Status (1)

Country Link
JP (1) JPS6425621A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04160921A (en) * 1990-10-25 1992-06-04 Nec Ic Microcomput Syst Ltd High impedance protection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04160921A (en) * 1990-10-25 1992-06-04 Nec Ic Microcomput Syst Ltd High impedance protection circuit

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