DE60218932T2 - Integrierte Schaltkreisstruktur - Google Patents

Integrierte Schaltkreisstruktur Download PDF

Info

Publication number
DE60218932T2
DE60218932T2 DE60218932T DE60218932T DE60218932T2 DE 60218932 T2 DE60218932 T2 DE 60218932T2 DE 60218932 T DE60218932 T DE 60218932T DE 60218932 T DE60218932 T DE 60218932T DE 60218932 T2 DE60218932 T2 DE 60218932T2
Authority
DE
Germany
Prior art keywords
row
column
circuit
diode
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60218932T
Other languages
German (de)
English (en)
Other versions
DE60218932D1 (de
Inventor
Carl Redwood City Taussig
Richard Palo Alto Elder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Application granted granted Critical
Publication of DE60218932D1 publication Critical patent/DE60218932D1/de
Publication of DE60218932T2 publication Critical patent/DE60218932T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/801—Interconnections on sidewalls of containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/91—Diode arrays, e.g. diode read-only memory array

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE60218932T 2001-06-05 2002-05-10 Integrierte Schaltkreisstruktur Expired - Lifetime DE60218932T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US875572 2001-06-05
US09/875,572 US6552409B2 (en) 2001-06-05 2001-06-05 Techniques for addressing cross-point diode memory arrays

Publications (2)

Publication Number Publication Date
DE60218932D1 DE60218932D1 (de) 2007-05-03
DE60218932T2 true DE60218932T2 (de) 2007-10-18

Family

ID=25366025

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60218932T Expired - Lifetime DE60218932T2 (de) 2001-06-05 2002-05-10 Integrierte Schaltkreisstruktur

Country Status (7)

Country Link
US (1) US6552409B2 (https=)
EP (1) EP1265286B1 (https=)
JP (1) JP2003007977A (https=)
KR (1) KR20020092823A (https=)
CN (1) CN1263135C (https=)
DE (1) DE60218932T2 (https=)
TW (1) TW564516B (https=)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673218A (en) 1996-03-05 1997-09-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6956757B2 (en) * 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
WO2002027768A2 (en) * 2000-09-27 2002-04-04 Nüp2 Incorporated Fabrication of semiconductor devices
US6639859B2 (en) * 2001-10-25 2003-10-28 Hewlett-Packard Development Company, L.P. Test array and method for testing memory arrays
US6683322B2 (en) 2002-03-01 2004-01-27 Hewlett-Packard Development Company, L.P. Flexible hybrid memory element
US6828685B2 (en) * 2002-06-14 2004-12-07 Hewlett-Packard Development Company, L.P. Memory device having a semiconducting polymer film
US7079442B2 (en) * 2002-08-02 2006-07-18 Unity Semiconductor Corporation Layout of driver sets in a cross point memory array
US6887792B2 (en) * 2002-09-17 2005-05-03 Hewlett-Packard Development Company, L.P. Embossed mask lithography
US6867132B2 (en) * 2002-09-17 2005-03-15 Hewlett-Packard Development Company, L.P. Large line conductive pads for interconnection of stackable circuitry
US6762094B2 (en) * 2002-09-27 2004-07-13 Hewlett-Packard Development Company, L.P. Nanometer-scale semiconductor devices and method of making
GB0229191D0 (en) * 2002-12-14 2003-01-22 Plastic Logic Ltd Embossing of polymer devices
US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US7394680B2 (en) 2003-03-18 2008-07-01 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode
US7400522B2 (en) 2003-03-18 2008-07-15 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
US7778062B2 (en) 2003-03-18 2010-08-17 Kabushiki Kaisha Toshiba Resistance change memory device
US7606059B2 (en) 2003-03-18 2009-10-20 Kabushiki Kaisha Toshiba Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
KR20060010763A (ko) * 2003-05-01 2006-02-02 퀸 메리 앤드 웨스트필드 컬리지 케이스화된 열 관리 장치 및 그 제조 방법
US20070034909A1 (en) * 2003-09-22 2007-02-15 James Stasiak Nanometer-scale semiconductor devices and method of making
SE526368C2 (sv) * 2003-10-30 2005-08-30 Infineon Technologies Ag Zener-Zap Minne
US6980465B2 (en) * 2003-12-19 2005-12-27 Hewlett-Packard Development Company, L.P. Addressing circuit for a cross-point memory array including cross-point resistive elements
US8148251B2 (en) 2004-01-30 2012-04-03 Hewlett-Packard Development Company, L.P. Forming a semiconductor device
JP4377751B2 (ja) * 2004-06-10 2009-12-02 シャープ株式会社 クロスポイント構造の半導体記憶装置及びその製造方法
KR100626009B1 (ko) * 2004-06-30 2006-09-20 삼성에스디아이 주식회사 박막 트랜지스터 구조체 및 이를 구비하는 평판디스플레이 장치
US20060006787A1 (en) * 2004-07-06 2006-01-12 David Champion Electronic device having a plurality of conductive beams
US7106639B2 (en) * 2004-09-01 2006-09-12 Hewlett-Packard Development Company, L.P. Defect management enabled PIRM and method
EP2348460B1 (en) * 2004-10-18 2014-04-23 Semiconductor Energy Laboratory Co, Ltd. Organic anti fuse memory
JP4880894B2 (ja) * 2004-11-17 2012-02-22 シャープ株式会社 半導体記憶装置の構造及びその製造方法
US7453755B2 (en) * 2005-07-01 2008-11-18 Sandisk 3D Llc Memory cell with high-K antifuse for reverse bias programming
KR100730254B1 (ko) 2005-09-16 2007-06-20 가부시끼가이샤 도시바 프로그램가능 저항 메모리 장치
US20070176255A1 (en) * 2006-01-31 2007-08-02 Franz Kreupl Integrated circuit arrangement
CN101401209B (zh) * 2006-03-10 2011-05-25 株式会社半导体能源研究所 存储元件以及半导体器件
JP5201853B2 (ja) * 2006-03-10 2013-06-05 株式会社半導体エネルギー研究所 半導体装置
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
US7486537B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
US7372753B1 (en) * 2006-10-19 2008-05-13 Unity Semiconductor Corporation Two-cycle sensing in a two-terminal memory array having leakage current
US7692951B2 (en) 2007-06-12 2010-04-06 Kabushiki Kaisha Toshiba Resistance change memory device with a variable resistance element formed of a first and a second composite compound
US20090086521A1 (en) * 2007-09-28 2009-04-02 Herner S Brad Multiple antifuse memory cells and methods to form, program, and sense the same
US7948094B2 (en) * 2007-10-22 2011-05-24 Rohm Co., Ltd. Semiconductor device
US7813157B2 (en) * 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory
US20090225621A1 (en) * 2008-03-05 2009-09-10 Shepard Daniel R Split decoder storage array and methods of forming the same
WO2009149061A2 (en) * 2008-06-02 2009-12-10 Contour Semiconductor, Inc. Diode decoder array with non-sequential layout and methods of forming the same
US8325556B2 (en) * 2008-10-07 2012-12-04 Contour Semiconductor, Inc. Sequencing decoder circuit
KR20110105257A (ko) * 2010-03-18 2011-09-26 삼성전자주식회사 적층 구조를 갖는 반도체 메모리 장치 및 에러 정정 방법
KR20110105255A (ko) * 2010-03-18 2011-09-26 삼성전자주식회사 적층 구조를 갖는 반도체 메모리 장치 및 그 제조 방법
US8866121B2 (en) 2011-07-29 2014-10-21 Sandisk 3D Llc Current-limiting layer and a current-reducing layer in a memory device
US8659001B2 (en) 2011-09-01 2014-02-25 Sandisk 3D Llc Defect gradient to boost nonvolatile memory performance
US8637413B2 (en) 2011-12-02 2014-01-28 Sandisk 3D Llc Nonvolatile resistive memory element with a passivated switching layer
US8698119B2 (en) 2012-01-19 2014-04-15 Sandisk 3D Llc Nonvolatile memory device using a tunnel oxide as a current limiter element
US8686386B2 (en) 2012-02-17 2014-04-01 Sandisk 3D Llc Nonvolatile memory device using a varistor as a current limiter element
US20140241031A1 (en) 2013-02-28 2014-08-28 Sandisk 3D Llc Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same
TWI497899B (zh) 2013-08-05 2015-08-21 Ind Tech Res Inst 機構式編碼器
KR20180005033A (ko) * 2016-07-05 2018-01-15 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
JP7086961B2 (ja) * 2016-08-29 2022-06-20 スカイワークス ソリューションズ，インコーポレイテッド ヒューズ状態検出回路、デバイス及び方法
WO2019059952A1 (en) * 2017-09-25 2019-03-28 Intel Corporation INTEGRATION OF HIGH-DENSITY CROSS-POINT MEMORY AND CMOS LOGIC FOR LOW-LOW AND HIGH-DENSITY ENVM AND EDRAM APPLICATIONS
TWI758077B (zh) * 2021-01-21 2022-03-11 凌北卿 具有pn二極體之非揮發性記憶體元件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4089734A (en) * 1974-09-16 1978-05-16 Raytheon Company Integrated circuit fusing technique
US4677742A (en) * 1983-01-18 1987-07-07 Energy Conversion Devices, Inc. Electronic matrix arrays and method for making the same
US4569120A (en) * 1983-03-07 1986-02-11 Signetics Corporation Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation
US4795657A (en) * 1984-04-13 1989-01-03 Energy Conversion Devices, Inc. Method of fabricating a programmable array
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
US5311053A (en) * 1991-06-12 1994-05-10 Aptix Corporation Interconnection network
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
JPH09331029A (ja) * 1996-06-12 1997-12-22 Ricoh Co Ltd 半導体メモリ装置とその製造方法
NO304956B1 (no) * 1997-07-22 1999-03-08 Opticom As Elektrodeanordning uten og med et funksjonselement, samt en elektrodeinnretning dannet av elektrodeanordninger med funksjonselement og anvendelser derav

Also Published As

Publication number Publication date
CN1389919A (zh) 2003-01-08
EP1265286A2 (en) 2002-12-11
US20020192895A1 (en) 2002-12-19
JP2003007977A (ja) 2003-01-10
KR20020092823A (ko) 2002-12-12
CN1263135C (zh) 2006-07-05
EP1265286A3 (en) 2003-12-03
DE60218932D1 (de) 2007-05-03
TW564516B (en) 2003-12-01
US6552409B2 (en) 2003-04-22
EP1265286B1 (en) 2007-03-21

Similar Documents

Publication Publication Date Title
DE60218932T2 (de) Integrierte Schaltkreisstruktur
DE69803782T2 (de) Festwertspeicher und festwertspeicheranordnungen
DE69824293T2 (de) Ferroelektrische datenverarbeitungsanordnung
DE60129540T2 (de) Multidimensionale adressierungsarchitektur für elektronische anordnungen
DE102004040506A1 (de) Adressierschaltung für ein Kreuzungspunkt-Speicherarray, das Kreuzungspunkt-Widerstandselemente umfasst
DE60224622T2 (de) Einmal programmierbarer Speicher
DE60130586T2 (de) Speicherzelle
DE69734007T2 (de) Struktur für programmierbare metallisierzelle und herstellungsverfahren dazu
DE60219719T2 (de) Speichermatrix und Herstellungsverfahren
US6919633B2 (en) Multi-section foldable memory device
DE602004005333T2 (de) Planarer polymer-speicherbaustein
DE1954966C3 (de) Elektrische Speichermatrix in Kompaktbauweise
US8183554B2 (en) Symmetrical programmable memresistor crossbar structure
KR20020092828A (ko) 데이터 저장 장치, 메모리 모듈, 메모리 시스템, 디지털데이터 메모리 시스템
DE60304209T2 (de) Magnettunnelsperrschichtspeicherzellenarchitektur
DE2300847B2 (de) Halbleiterfestwertspeicher
JP2003059282A (ja) クロスポイントダイオードメモリアレイの並列アクセス
DE3408747A1 (de) Universell verwendbare anordnung von bauelementen fuer variable beschaltung
DE60201135T2 (de) Adressierbare Speichervorrichtung mit einer Anzeige
DE3751396T2 (de) Thermischer Kopf.
DE60306029T2 (de) Speichervorrichtung mit vernetztem Zellenfeld
DE102021107107A1 (de) Schaltungsstruktur und verfahren zur speicherung im speicher mit speicherzelle und mram-stapel
WO2006029594A1 (de) Halbleiterspeicherbauelement
DE60207298T2 (de) Klappspeicherschichten
DE102005040557A1 (de) Integrierte Speicherschaltung mit einem resistiven Speicherelement sowie ein Verfahren zur Herstellung einer solchen Speicherschaltung

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, US

8364 No opposition during term of opposition