KR20020092823A - 집적 회로 구조 및 집적 회로 연결 소자 형성 방법과,회로 형성 방법과, 어드레싱 회로 및 어드레싱 회로 형성방법 - Google Patents

집적 회로 구조 및 집적 회로 연결 소자 형성 방법과,회로 형성 방법과, 어드레싱 회로 및 어드레싱 회로 형성방법 Download PDF

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Publication number
KR20020092823A
KR20020092823A KR1020020031268A KR20020031268A KR20020092823A KR 20020092823 A KR20020092823 A KR 20020092823A KR 1020020031268 A KR1020020031268 A KR 1020020031268A KR 20020031268 A KR20020031268 A KR 20020031268A KR 20020092823 A KR20020092823 A KR 20020092823A
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KR
South Korea
Prior art keywords
circuit
conductor
line
memory
layer
Prior art date
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Ceased
Application number
KR1020020031268A
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English (en)
Korean (ko)
Inventor
타우시그칼
엘더리챠드
Original Assignee
휴렛-팩커드 컴퍼니(델라웨어주법인)
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Publication of KR20020092823A publication Critical patent/KR20020092823A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/801—Interconnections on sidewalls of containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/91—Diode arrays, e.g. diode read-only memory array

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
KR1020020031268A 2001-06-05 2002-06-04 집적 회로 구조 및 집적 회로 연결 소자 형성 방법과,회로 형성 방법과, 어드레싱 회로 및 어드레싱 회로 형성방법 Ceased KR20020092823A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/875,572 US6552409B2 (en) 2001-06-05 2001-06-05 Techniques for addressing cross-point diode memory arrays
US09/875,572 2001-06-05

Publications (1)

Publication Number Publication Date
KR20020092823A true KR20020092823A (ko) 2002-12-12

Family

ID=25366025

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020031268A Ceased KR20020092823A (ko) 2001-06-05 2002-06-04 집적 회로 구조 및 집적 회로 연결 소자 형성 방법과,회로 형성 방법과, 어드레싱 회로 및 어드레싱 회로 형성방법

Country Status (7)

Country Link
US (1) US6552409B2 (https=)
EP (1) EP1265286B1 (https=)
JP (1) JP2003007977A (https=)
KR (1) KR20020092823A (https=)
CN (1) CN1263135C (https=)
DE (1) DE60218932T2 (https=)
TW (1) TW564516B (https=)

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US7079442B2 (en) * 2002-08-02 2006-07-18 Unity Semiconductor Corporation Layout of driver sets in a cross point memory array
US6887792B2 (en) * 2002-09-17 2005-05-03 Hewlett-Packard Development Company, L.P. Embossed mask lithography
US6867132B2 (en) * 2002-09-17 2005-03-15 Hewlett-Packard Development Company, L.P. Large line conductive pads for interconnection of stackable circuitry
US6762094B2 (en) * 2002-09-27 2004-07-13 Hewlett-Packard Development Company, L.P. Nanometer-scale semiconductor devices and method of making
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US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US7394680B2 (en) 2003-03-18 2008-07-01 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode
US7400522B2 (en) 2003-03-18 2008-07-15 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
US7778062B2 (en) 2003-03-18 2010-08-17 Kabushiki Kaisha Toshiba Resistance change memory device
US7606059B2 (en) 2003-03-18 2009-10-20 Kabushiki Kaisha Toshiba Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
KR20060010763A (ko) * 2003-05-01 2006-02-02 퀸 메리 앤드 웨스트필드 컬리지 케이스화된 열 관리 장치 및 그 제조 방법
US20070034909A1 (en) * 2003-09-22 2007-02-15 James Stasiak Nanometer-scale semiconductor devices and method of making
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US6980465B2 (en) * 2003-12-19 2005-12-27 Hewlett-Packard Development Company, L.P. Addressing circuit for a cross-point memory array including cross-point resistive elements
US8148251B2 (en) 2004-01-30 2012-04-03 Hewlett-Packard Development Company, L.P. Forming a semiconductor device
JP4377751B2 (ja) * 2004-06-10 2009-12-02 シャープ株式会社 クロスポイント構造の半導体記憶装置及びその製造方法
KR100626009B1 (ko) * 2004-06-30 2006-09-20 삼성에스디아이 주식회사 박막 트랜지스터 구조체 및 이를 구비하는 평판디스플레이 장치
US20060006787A1 (en) * 2004-07-06 2006-01-12 David Champion Electronic device having a plurality of conductive beams
US7106639B2 (en) * 2004-09-01 2006-09-12 Hewlett-Packard Development Company, L.P. Defect management enabled PIRM and method
EP2348460B1 (en) * 2004-10-18 2014-04-23 Semiconductor Energy Laboratory Co, Ltd. Organic anti fuse memory
JP4880894B2 (ja) * 2004-11-17 2012-02-22 シャープ株式会社 半導体記憶装置の構造及びその製造方法
US7453755B2 (en) * 2005-07-01 2008-11-18 Sandisk 3D Llc Memory cell with high-K antifuse for reverse bias programming
KR100730254B1 (ko) 2005-09-16 2007-06-20 가부시끼가이샤 도시바 프로그램가능 저항 메모리 장치
US20070176255A1 (en) * 2006-01-31 2007-08-02 Franz Kreupl Integrated circuit arrangement
CN101401209B (zh) * 2006-03-10 2011-05-25 株式会社半导体能源研究所 存储元件以及半导体器件
JP5201853B2 (ja) * 2006-03-10 2013-06-05 株式会社半導体エネルギー研究所 半導体装置
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
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US7372753B1 (en) * 2006-10-19 2008-05-13 Unity Semiconductor Corporation Two-cycle sensing in a two-terminal memory array having leakage current
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Also Published As

Publication number Publication date
CN1389919A (zh) 2003-01-08
EP1265286A2 (en) 2002-12-11
DE60218932T2 (de) 2007-10-18
US20020192895A1 (en) 2002-12-19
JP2003007977A (ja) 2003-01-10
CN1263135C (zh) 2006-07-05
EP1265286A3 (en) 2003-12-03
DE60218932D1 (de) 2007-05-03
TW564516B (en) 2003-12-01
US6552409B2 (en) 2003-04-22
EP1265286B1 (en) 2007-03-21

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