DE60218932T2 - Integrierte Schaltkreisstruktur - Google Patents

Integrierte Schaltkreisstruktur Download PDF

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Publication number
DE60218932T2
DE60218932T2 DE60218932T DE60218932T DE60218932T2 DE 60218932 T2 DE60218932 T2 DE 60218932T2 DE 60218932 T DE60218932 T DE 60218932T DE 60218932 T DE60218932 T DE 60218932T DE 60218932 T2 DE60218932 T2 DE 60218932T2
Authority
DE
Germany
Prior art keywords
row
column
circuit
diode
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60218932T
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German (de)
English (en)
Other versions
DE60218932D1 (de
Inventor
Carl Redwood City Taussig
Richard Palo Alto Elder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
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Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of DE60218932D1 publication Critical patent/DE60218932D1/de
Application granted granted Critical
Publication of DE60218932T2 publication Critical patent/DE60218932T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/801—Interconnections on sidewalls of containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/91—Diode arrays, e.g. diode read-only memory array

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE60218932T 2001-06-05 2002-05-10 Integrierte Schaltkreisstruktur Expired - Lifetime DE60218932T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/875,572 US6552409B2 (en) 2001-06-05 2001-06-05 Techniques for addressing cross-point diode memory arrays
US875572 2001-06-05

Publications (2)

Publication Number Publication Date
DE60218932D1 DE60218932D1 (de) 2007-05-03
DE60218932T2 true DE60218932T2 (de) 2007-10-18

Family

ID=25366025

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60218932T Expired - Lifetime DE60218932T2 (de) 2001-06-05 2002-05-10 Integrierte Schaltkreisstruktur

Country Status (7)

Country Link
US (1) US6552409B2 (enExample)
EP (1) EP1265286B1 (enExample)
JP (1) JP2003007977A (enExample)
KR (1) KR20020092823A (enExample)
CN (1) CN1263135C (enExample)
DE (1) DE60218932T2 (enExample)
TW (1) TW564516B (enExample)

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US6887792B2 (en) * 2002-09-17 2005-05-03 Hewlett-Packard Development Company, L.P. Embossed mask lithography
US6762094B2 (en) * 2002-09-27 2004-07-13 Hewlett-Packard Development Company, L.P. Nanometer-scale semiconductor devices and method of making
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US7778062B2 (en) 2003-03-18 2010-08-17 Kabushiki Kaisha Toshiba Resistance change memory device
US7606059B2 (en) 2003-03-18 2009-10-20 Kabushiki Kaisha Toshiba Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
US7400522B2 (en) 2003-03-18 2008-07-15 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
US20070090519A1 (en) * 2003-05-01 2007-04-26 Carter Antony A Encased thermal management device and method of making such a device
US20070034909A1 (en) * 2003-09-22 2007-02-15 James Stasiak Nanometer-scale semiconductor devices and method of making
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US6980465B2 (en) * 2003-12-19 2005-12-27 Hewlett-Packard Development Company, L.P. Addressing circuit for a cross-point memory array including cross-point resistive elements
US8148251B2 (en) * 2004-01-30 2012-04-03 Hewlett-Packard Development Company, L.P. Forming a semiconductor device
JP4377751B2 (ja) * 2004-06-10 2009-12-02 シャープ株式会社 クロスポイント構造の半導体記憶装置及びその製造方法
KR100626009B1 (ko) * 2004-06-30 2006-09-20 삼성에스디아이 주식회사 박막 트랜지스터 구조체 및 이를 구비하는 평판디스플레이 장치
US20060006787A1 (en) * 2004-07-06 2006-01-12 David Champion Electronic device having a plurality of conductive beams
US7106639B2 (en) * 2004-09-01 2006-09-12 Hewlett-Packard Development Company, L.P. Defect management enabled PIRM and method
KR101201698B1 (ko) * 2004-10-18 2012-11-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP4880894B2 (ja) * 2004-11-17 2012-02-22 シャープ株式会社 半導体記憶装置の構造及びその製造方法
US7453755B2 (en) * 2005-07-01 2008-11-18 Sandisk 3D Llc Memory cell with high-K antifuse for reverse bias programming
KR100730254B1 (ko) 2005-09-16 2007-06-20 가부시끼가이샤 도시바 프로그램가능 저항 메모리 장치
US20070176255A1 (en) * 2006-01-31 2007-08-02 Franz Kreupl Integrated circuit arrangement
JP5201853B2 (ja) * 2006-03-10 2013-06-05 株式会社半導体エネルギー研究所 半導体装置
KR101316558B1 (ko) * 2006-03-10 2013-10-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 메모리 소자 및 반도체 장치
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states
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US7372753B1 (en) * 2006-10-19 2008-05-13 Unity Semiconductor Corporation Two-cycle sensing in a two-terminal memory array having leakage current
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US20090086521A1 (en) * 2007-09-28 2009-04-02 Herner S Brad Multiple antifuse memory cells and methods to form, program, and sense the same
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Also Published As

Publication number Publication date
CN1389919A (zh) 2003-01-08
US6552409B2 (en) 2003-04-22
TW564516B (en) 2003-12-01
CN1263135C (zh) 2006-07-05
EP1265286A2 (en) 2002-12-11
JP2003007977A (ja) 2003-01-10
US20020192895A1 (en) 2002-12-19
EP1265286B1 (en) 2007-03-21
KR20020092823A (ko) 2002-12-12
EP1265286A3 (en) 2003-12-03
DE60218932D1 (de) 2007-05-03

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, US

8364 No opposition during term of opposition