DE60216182D1 - Verfahren zur Herstellung einer gedruckten Leiterplatte - Google Patents

Verfahren zur Herstellung einer gedruckten Leiterplatte

Info

Publication number
DE60216182D1
DE60216182D1 DE60216182T DE60216182T DE60216182D1 DE 60216182 D1 DE60216182 D1 DE 60216182D1 DE 60216182 T DE60216182 T DE 60216182T DE 60216182 T DE60216182 T DE 60216182T DE 60216182 D1 DE60216182 D1 DE 60216182D1
Authority
DE
Germany
Prior art keywords
substrate
conductive layer
producing
circuit patterns
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60216182T
Other languages
English (en)
Other versions
DE60216182T2 (de
Inventor
Toshiyuki Suzuki
Kazuya Nakagawa
Mitsuru Kobayashi
Eiji Shiohama
Masaru Sugimoto
Hideyoshi Kimura
Takuma Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001151383A external-priority patent/JP4131094B2/ja
Priority claimed from JP2001151382A external-priority patent/JP4207399B2/ja
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Application granted granted Critical
Publication of DE60216182D1 publication Critical patent/DE60216182D1/de
Publication of DE60216182T2 publication Critical patent/DE60216182T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0293—Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09127—PCB or component having an integral separable or breakable part
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
DE60216182T 2001-05-21 2002-05-21 Verfahren zur Herstellung einer gedruckten Leiterplatte Expired - Lifetime DE60216182T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2001151383A JP4131094B2 (ja) 2001-05-21 2001-05-21 配線基板の製造方法
JP2001151382 2001-05-21
JP2001151382A JP4207399B2 (ja) 2001-05-21 2001-05-21 配線基板の製造方法
JP2001151383 2001-05-21

Publications (2)

Publication Number Publication Date
DE60216182D1 true DE60216182D1 (de) 2007-01-04
DE60216182T2 DE60216182T2 (de) 2007-09-13

Family

ID=26615433

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60216182T Expired - Lifetime DE60216182T2 (de) 2001-05-21 2002-05-21 Verfahren zur Herstellung einer gedruckten Leiterplatte

Country Status (8)

Country Link
US (1) US6796027B2 (de)
EP (2) EP1713312A3 (de)
KR (1) KR100492498B1 (de)
CN (1) CN1198492C (de)
AT (1) ATE346483T1 (de)
CA (1) CA2387012C (de)
DE (1) DE60216182T2 (de)
TW (1) TWI235024B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6905589B2 (en) * 2003-02-24 2005-06-14 Endicott Interconnect Technologies, Inc. Circuitized substrate and method of making same
US7078816B2 (en) * 2004-03-31 2006-07-18 Endicott Interconnect Technologies, Inc. Circuitized substrate
US7145221B2 (en) * 2004-03-31 2006-12-05 Endicott Interconnect Technologies, Inc. Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same
US7270845B2 (en) * 2004-03-31 2007-09-18 Endicott Interconnect Technologies, Inc. Dielectric composition for forming dielectric layer for use in circuitized substrates
CN100458521C (zh) * 2005-04-26 2009-02-04 友达光电股份有限公司 背光模块、串接模块及其导电块
US20070146974A1 (en) * 2005-12-23 2007-06-28 Cleopatra Cabuz Electrical circuit pattern design by injection mold
US20130048342A1 (en) * 2011-08-23 2013-02-28 Tyco Electronics Corporation Circuit board
CN103384452A (zh) * 2012-05-02 2013-11-06 力达通讯股份有限公司 线路图案的制造方法
DE102013113009A1 (de) 2013-11-25 2015-05-28 Osram Opto Semiconductors Gmbh Gehäuse für einen Halbleiterchip, Gehäuseverbund, Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements
CN109479373A (zh) 2016-07-07 2019-03-15 莫列斯有限公司 模塑互连器件及制造其的方法
US10184189B2 (en) 2016-07-18 2019-01-22 ECSI Fibrotools, Inc. Apparatus and method of contact electroplating of isolated structures
CN108242477B (zh) * 2016-12-27 2020-03-24 中国科学院上海高等研究院 层转移单晶硅薄膜用籽晶衬底的微接触湿法刻蚀制备方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3491197A (en) * 1966-12-30 1970-01-20 Texas Instruments Inc Universal printed circuit board
US3601522A (en) * 1970-06-18 1971-08-24 American Lava Corp Composite ceramic package breakaway notch
DE2622766A1 (de) * 1976-05-21 1977-11-24 Westfaelische Metall Industrie Verfahren zur herstellung einer leiterplatte
US4604799A (en) 1982-09-03 1986-08-12 John Fluke Mfg. Co., Inc. Method of making molded circuit board
US4861640A (en) 1982-09-03 1989-08-29 John Fluke Mfg. Co., Inc. Molded circuit board and manufacturing method therefor
DE3843230C1 (en) * 1988-12-22 1989-09-21 W.C. Heraeus Gmbh, 6450 Hanau, De Process for making a metallic pattern on a base, in particular for the laser structuring of conductor tracks
JPH03183190A (ja) * 1989-12-12 1991-08-09 Satosen Co Ltd プリント配線板の製造方法
GB8928640D0 (en) * 1989-12-19 1990-02-21 Technology Applic Company Limi Electrical conductors of conductive resin
US4985116A (en) 1990-02-23 1991-01-15 Mint-Pac Technologies, Inc. Three dimensional plating or etching process and masks therefor
US5112230A (en) * 1991-01-14 1992-05-12 Motorola, Inc. Reconfigurable substrate for electric circuit connections
JPH0582959A (ja) * 1991-09-20 1993-04-02 Hitachi Chem Co Ltd 導電性回路を有する成形品
JPH0637427A (ja) * 1992-07-17 1994-02-10 Fujitsu Ltd 銅ポリイミド配線板の製造方法並びにその構造
JPH0684896A (ja) * 1992-09-02 1994-03-25 Nippon Telegr & Teleph Corp <Ntt> 配線構造体の製法
JP3153682B2 (ja) 1993-08-26 2001-04-09 松下電工株式会社 回路板の製造方法
WO1996003851A1 (en) * 1994-07-25 1996-02-08 Minnesota Mining And Manufacturing Company Microridge abrasion for selective metalization
JPH08148810A (ja) * 1994-11-16 1996-06-07 Hitachi Chem Co Ltd プリント配線板の製造法
JPH09172133A (ja) * 1995-12-19 1997-06-30 Sumitomo Kinzoku Electro Device:Kk セラミックパッケージ内部配線露出部のメッキ方法
JP2803717B2 (ja) * 1996-03-21 1998-09-24 日本電気株式会社 チップ状遮断部品及びその回路修復装置
DE19614706C2 (de) * 1996-04-13 1998-02-26 Telefunken Microelectron Verfahren zur Herstellung von elektrisch leitenden Durchführungen in metallisierten Kunststoffgehäusen
JP2919817B2 (ja) * 1997-10-20 1999-07-19 イビデン株式会社 プリント配線板の製造方法
JP3324982B2 (ja) * 1998-03-26 2002-09-17 松下電工株式会社 回路板の製造方法
JP2000101218A (ja) * 1998-09-22 2000-04-07 Matsushita Electric Works Ltd 回路板製造法

Also Published As

Publication number Publication date
EP1713312A2 (de) 2006-10-18
EP1713312A3 (de) 2009-01-14
US20020172019A1 (en) 2002-11-21
DE60216182T2 (de) 2007-09-13
EP1261243A3 (de) 2003-05-02
KR100492498B1 (ko) 2005-05-30
EP1261243A2 (de) 2002-11-27
US6796027B2 (en) 2004-09-28
CA2387012A1 (en) 2002-11-21
CA2387012C (en) 2006-07-25
CN1387397A (zh) 2002-12-25
ATE346483T1 (de) 2006-12-15
CN1198492C (zh) 2005-04-20
TWI235024B (en) 2005-06-21
EP1261243B1 (de) 2006-11-22
KR20020088376A (ko) 2002-11-27

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Legal Events

Date Code Title Description
8381 Inventor (new situation)

Inventor name: SUZUKI, TOSHIYUKI, KADOMA-SHI, OSAKA 571-8686, JP

Inventor name: NAKAGAWA, KAZUYA, KADOMA-SHI, OSAKA 571-8686, JP

Inventor name: KOBAYASHI, MITSURU, KADOMA-SHI, OSAKA 571-8686, JP

Inventor name: SHIOHAMA, EIJI, KADOMA-SHI, OSAKA 571-8686, JP

Inventor name: SUGIMOTO, MASARU, KADOMA-SHI, OSAKA 571-8686, JP

Inventor name: KIMURA, HIDEYOSHI, KADOMA-SHI, OSAKA 571-8686, JP

Inventor name: HASHIMOTO, TAKUMA, KADOMA-SHI, OSAKA 571-8686, JP

8364 No opposition during term of opposition