DE602005010411D1 - Halbleiterspeicher mit redundanten Zeilen und Spalten und flexibler Redundanzarchitektur - Google Patents

Halbleiterspeicher mit redundanten Zeilen und Spalten und flexibler Redundanzarchitektur

Info

Publication number
DE602005010411D1
DE602005010411D1 DE602005010411T DE602005010411T DE602005010411D1 DE 602005010411 D1 DE602005010411 D1 DE 602005010411D1 DE 602005010411 T DE602005010411 T DE 602005010411T DE 602005010411 T DE602005010411 T DE 602005010411T DE 602005010411 D1 DE602005010411 D1 DE 602005010411D1
Authority
DE
Germany
Prior art keywords
columns
semiconductor memory
redundant rows
redundancy architecture
flexible redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005010411T
Other languages
English (en)
Inventor
Kaoru Mori
Yoshiaki Okuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602005010411D1 publication Critical patent/DE602005010411D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares
DE602005010411T 2005-06-30 2005-10-26 Halbleiterspeicher mit redundanten Zeilen und Spalten und flexibler Redundanzarchitektur Active DE602005010411D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005191333A JP4607685B2 (ja) 2005-06-30 2005-06-30 半導体メモリ

Publications (1)

Publication Number Publication Date
DE602005010411D1 true DE602005010411D1 (de) 2008-11-27

Family

ID=37085843

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005010411T Active DE602005010411D1 (de) 2005-06-30 2005-10-26 Halbleiterspeicher mit redundanten Zeilen und Spalten und flexibler Redundanzarchitektur

Country Status (7)

Country Link
US (2) US7196951B2 (de)
EP (2) EP1887582B1 (de)
JP (1) JP4607685B2 (de)
KR (1) KR100756258B1 (de)
CN (2) CN101430937B (de)
DE (1) DE602005010411D1 (de)
TW (1) TWI287235B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101063571B1 (ko) * 2008-12-08 2011-09-07 주식회사 하이닉스반도체 페이지 버퍼 회로 및 이를 구비한 불휘발성 메모리 소자와 그 동작 방법
US8238178B2 (en) 2010-02-12 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Redundancy circuits and operating methods thereof
KR102597291B1 (ko) * 2016-11-07 2023-11-06 에스케이하이닉스 주식회사 리페어 제어 장치 및 이를 포함하는 반도체 장치
US11568229B2 (en) * 2018-07-11 2023-01-31 Silicon Storage Technology, Inc. Redundant memory access for rows or columns containing faulty memory cells in analog neural memory in deep learning artificial neural network
JP6804493B2 (ja) 2018-07-19 2020-12-23 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． メモリデバイス及びメモリ周辺回路
TWI713044B (zh) * 2018-08-16 2020-12-11 華邦電子股份有限公司 記憶體裝置以及記憶體周邊電路
CN110867205B (zh) * 2018-08-27 2021-10-08 华邦电子股份有限公司 存储器装置以及存储器周边电路
CN111192621A (zh) * 2018-11-14 2020-05-22 长鑫存储技术有限公司 字线控制方法、字线控制电路装置以及半导体存储器
KR20200101651A (ko) * 2019-02-20 2020-08-28 에스케이하이닉스 주식회사 메모리 및 메모리의 동작 방법
KR102669502B1 (ko) 2019-07-09 2024-05-27 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법
CN112149548B (zh) * 2020-09-17 2022-10-21 宁夏宁电电力设计有限公司 一种适用于端子排的cad图纸智能录入和识别方法及其装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265055A (en) * 1988-10-07 1993-11-23 Hitachi, Ltd. Semiconductor memory having redundancy circuit
KR950015041B1 (ko) * 1992-11-23 1995-12-21 삼성전자주식회사 로우리던던시회로를 가지는 고집적 반도체 메모리 장치
JP3020077B2 (ja) * 1993-03-03 2000-03-15 株式会社日立製作所 半導体メモリ
JP3774500B2 (ja) * 1995-05-12 2006-05-17 株式会社ルネサステクノロジ 半導体記憶装置
JP3557022B2 (ja) * 1995-12-08 2004-08-25 株式会社東芝 半導体記憶装置
JPH10275493A (ja) * 1997-03-31 1998-10-13 Nec Corp 半導体記憶装置
US5831914A (en) * 1997-03-31 1998-11-03 International Business Machines Corporation Variable size redundancy replacement architecture to make a memory fault-tolerant
JPH10326496A (ja) * 1997-05-26 1998-12-08 Hitachi Ltd 半導体記憶装置
JPH10334690A (ja) * 1997-05-27 1998-12-18 Nec Corp 半導体記憶装置
JPH11250691A (ja) * 1998-02-27 1999-09-17 Toshiba Corp 半導体記憶装置
DE59903253D1 (de) 1998-04-17 2002-12-05 Infineon Technologies Ag Speicheranordnung mit redundanten speicherzellen und verfahren zum zugriff auf redundante speicherzellen
US6052318A (en) * 1998-12-22 2000-04-18 Siemens Aktiengesellschaft Repairable semiconductor memory circuit having parrel redundancy replacement wherein redundancy elements replace failed elements
JP2000235800A (ja) * 1999-02-12 2000-08-29 Mitsubishi Electric Corp 半導体記憶装置
JP2000268598A (ja) * 1999-03-18 2000-09-29 Toshiba Corp 半導体メモリのリダンダンシイ回路
JP2001093294A (ja) * 1999-09-24 2001-04-06 Hitachi Ltd 半導体装置
US6421284B1 (en) * 2000-05-26 2002-07-16 Hitachi, Limited Semiconductor device
JP2002008390A (ja) * 2000-06-16 2002-01-11 Fujitsu Ltd 冗長セルを有するメモリデバイス
TW594775B (en) * 2001-06-04 2004-06-21 Toshiba Corp Semiconductor memory device
KR100408714B1 (ko) 2001-06-28 2003-12-11 주식회사 하이닉스반도체 반도체 메모리 장치의 컬럼 리페어회로 및 방법
JP2003208796A (ja) * 2002-01-15 2003-07-25 Mitsubishi Electric Corp 薄膜磁性体記憶装置

Also Published As

Publication number Publication date
TW200701250A (en) 2007-01-01
KR100756258B1 (ko) 2007-09-07
CN101430937B (zh) 2012-09-05
EP1887582A3 (de) 2008-04-23
EP1887582A2 (de) 2008-02-13
US7362630B2 (en) 2008-04-22
US20070002647A1 (en) 2007-01-04
EP1742228B1 (de) 2008-10-15
US7196951B2 (en) 2007-03-27
TWI287235B (en) 2007-09-21
CN1892903A (zh) 2007-01-10
EP1887582B1 (de) 2011-10-19
US20070195620A1 (en) 2007-08-23
KR20070003512A (ko) 2007-01-05
CN100527271C (zh) 2009-08-12
CN101430937A (zh) 2009-05-13
JP4607685B2 (ja) 2011-01-05
EP1742228A1 (de) 2007-01-10
JP2007012165A (ja) 2007-01-18

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE