DE602004018847D1 - Halbleiter-speicherbaustein - Google Patents

Halbleiter-speicherbaustein

Info

Publication number
DE602004018847D1
DE602004018847D1 DE602004018847T DE602004018847T DE602004018847D1 DE 602004018847 D1 DE602004018847 D1 DE 602004018847D1 DE 602004018847 T DE602004018847 T DE 602004018847T DE 602004018847 T DE602004018847 T DE 602004018847T DE 602004018847 D1 DE602004018847 D1 DE 602004018847D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory module
module
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004018847T
Other languages
English (en)
Inventor
Hiroyoshi Tomita
Shusaku Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602004018847D1 publication Critical patent/DE602004018847D1/de
Anticipated expiration legal-status Critical
Active legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
DE602004018847T 2004-07-16 2004-07-16 Halbleiter-speicherbaustein Active DE602004018847D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2004/010210 WO2006008796A1 (ja) 2004-07-16 2004-07-16 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE602004018847D1 true DE602004018847D1 (de) 2009-02-12

Family

ID=35784932

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004018847T Active DE602004018847D1 (de) 2004-07-16 2004-07-16 Halbleiter-speicherbaustein

Country Status (7)

Country Link
US (1) US7719915B2 (de)
EP (1) EP1770711B1 (de)
JP (1) JPWO2006008796A1 (de)
KR (2) KR100874179B1 (de)
CN (1) CN100550196C (de)
DE (1) DE602004018847D1 (de)
WO (1) WO2006008796A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7292490B1 (en) * 2005-09-08 2007-11-06 Gsi Technology, Inc. System and method for refreshing a DRAM device
KR100795005B1 (ko) 2006-06-09 2008-01-16 주식회사 하이닉스반도체 반도체 메모리 장치
KR100886180B1 (ko) * 2007-05-25 2009-02-27 엠텍비젼 주식회사 의사 스태틱 랜덤 액세스 메모리 장치, 메모리 장치 및의사 스태틱 랜덤 액세스 메모리 장치의 동작 방법
US9141561B2 (en) * 2012-10-25 2015-09-22 Texas Instruments Incorporated Master circuits having dynamic priority leads coupled with memory controller
US10916293B1 (en) * 2020-01-21 2021-02-09 Elite Semiconductor Memory Technology Inc. Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1166843A (ja) * 1997-08-08 1999-03-09 Mitsubishi Electric Corp 半導体記憶装置
KR100329734B1 (ko) * 1998-04-03 2002-06-20 박종섭 어드레스입력및데이터입력용으로동일단자를겸용하는반도체메모리장치
JP4408500B2 (ja) * 1999-11-18 2010-02-03 株式会社ルネサステクノロジ 半導体集積回路
JP2001216800A (ja) * 2000-02-01 2001-08-10 Fujitsu Ltd 半導体集積回路および半導体集積回路の特性調整方法
JP3778417B2 (ja) * 2000-02-29 2006-05-24 富士通株式会社 半導体記憶装置
JP3636968B2 (ja) * 2000-06-05 2005-04-06 エルピーダメモリ株式会社 半導体装置及びそのテスト方法
JP4749538B2 (ja) * 2000-12-11 2011-08-17 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6587395B2 (en) * 2001-05-30 2003-07-01 Fujitsu Limited System to set burst mode in a device
JP4768163B2 (ja) * 2001-08-03 2011-09-07 富士通セミコンダクター株式会社 半導体メモリ
JP4249412B2 (ja) * 2001-12-27 2009-04-02 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
JP4078119B2 (ja) * 2002-04-15 2008-04-23 富士通株式会社 半導体メモリ
JP4246971B2 (ja) * 2002-07-15 2009-04-02 富士通マイクロエレクトロニクス株式会社 半導体メモリ
JP3998539B2 (ja) * 2002-08-28 2007-10-31 富士通株式会社 半導体記憶装置
JP2004199842A (ja) * 2002-12-20 2004-07-15 Nec Micro Systems Ltd 半導体記憶装置及びその制御方法

Also Published As

Publication number Publication date
JPWO2006008796A1 (ja) 2008-05-01
KR100909411B1 (ko) 2009-07-24
EP1770711A1 (de) 2007-04-04
EP1770711B1 (de) 2008-12-31
CN1989570A (zh) 2007-06-27
KR100874179B1 (ko) 2008-12-15
KR20070021321A (ko) 2007-02-22
KR20080102274A (ko) 2008-11-24
CN100550196C (zh) 2009-10-14
WO2006008796A1 (ja) 2006-01-26
US7719915B2 (en) 2010-05-18
EP1770711A4 (de) 2007-08-15
US20070109897A1 (en) 2007-05-17

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE