DE60140166D1 - Halbleiterspeicheranordnung mit SRAM Schnittstellevorrichtung - Google Patents

Halbleiterspeicheranordnung mit SRAM Schnittstellevorrichtung

Info

Publication number
DE60140166D1
DE60140166D1 DE60140166T DE60140166T DE60140166D1 DE 60140166 D1 DE60140166 D1 DE 60140166D1 DE 60140166 T DE60140166 T DE 60140166T DE 60140166 T DE60140166 T DE 60140166T DE 60140166 D1 DE60140166 D1 DE 60140166D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
sram interface
memory device
interface device
sram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60140166T
Other languages
English (en)
Inventor
Hitoshi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Application granted granted Critical
Publication of DE60140166D1 publication Critical patent/DE60140166D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE60140166T 2000-11-06 2001-08-20 Halbleiterspeicheranordnung mit SRAM Schnittstellevorrichtung Expired - Lifetime DE60140166D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000338057A JP2002150768A (ja) 2000-11-06 2000-11-06 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE60140166D1 true DE60140166D1 (de) 2009-11-26

Family

ID=18813336

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60140166T Expired - Lifetime DE60140166D1 (de) 2000-11-06 2001-08-20 Halbleiterspeicheranordnung mit SRAM Schnittstellevorrichtung

Country Status (6)

Country Link
US (1) US6631094B2 (de)
EP (1) EP1204118B1 (de)
JP (1) JP2002150768A (de)
KR (1) KR100741331B1 (de)
DE (1) DE60140166D1 (de)
TW (1) TW525192B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324103B2 (en) * 1998-11-11 2001-11-27 Hitachi, Ltd. Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
JP2010272204A (ja) * 2000-04-14 2010-12-02 Renesas Electronics Corp 半導体記憶装置
KR100487919B1 (ko) * 2002-08-30 2005-05-09 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 제어 장치
KR100482995B1 (ko) * 2002-09-06 2005-04-15 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치
US6956789B2 (en) * 2002-09-16 2005-10-18 Texas Instruments Incorporated Cycle ready circuit for self-clocking memory device
US6920524B2 (en) * 2003-02-03 2005-07-19 Micron Technology, Inc. Detection circuit for mixed asynchronous and synchronous memory operation
JP2005108327A (ja) 2003-09-30 2005-04-21 Toshiba Corp 半導体集積回路装置及びそのアクセス方法
KR100586558B1 (ko) * 2005-04-07 2006-06-08 주식회사 하이닉스반도체 컬럼 경로회로
JP4808070B2 (ja) * 2006-05-18 2011-11-02 富士通セミコンダクター株式会社 半導体メモリおよび半導体メモリの動作方法
JP5205992B2 (ja) * 2008-01-30 2013-06-05 富士通セミコンダクター株式会社 半導体メモリおよびメモリシステム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63155494A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 擬似スタテイツクメモリ装置
US5450552A (en) * 1987-08-17 1995-09-12 Nec Corporation Expanded address bus system for providing address signals to expanding devices
JPH0750556A (ja) * 1993-08-09 1995-02-21 Fujitsu Ltd フリップフロップ型増幅回路
US5592435A (en) * 1994-06-03 1997-01-07 Intel Corporation Pipelined read architecture for memory
US6122203A (en) * 1998-06-29 2000-09-19 Cypress Semiconductor Corp. Method, architecture and circuit for writing to and reading from a memory during a single cycle
JP3615423B2 (ja) * 1999-07-02 2005-02-02 シャープ株式会社 半導体記憶装置
JP4555416B2 (ja) * 1999-09-22 2010-09-29 富士通セミコンダクター株式会社 半導体集積回路およびその制御方法

Also Published As

Publication number Publication date
KR20020035427A (ko) 2002-05-11
US20020054533A1 (en) 2002-05-09
KR100741331B1 (ko) 2007-07-23
JP2002150768A (ja) 2002-05-24
EP1204118A2 (de) 2002-05-08
US6631094B2 (en) 2003-10-07
EP1204118A3 (de) 2003-05-14
TW525192B (en) 2003-03-21
EP1204118B1 (de) 2009-10-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE