DE60101159D1 - Herstellungsmethode eines stapelchip-ic-gehäuses auf scheibenebene - Google Patents

Herstellungsmethode eines stapelchip-ic-gehäuses auf scheibenebene

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Publication number
DE60101159D1
DE60101159D1 DE60101159T DE60101159T DE60101159D1 DE 60101159 D1 DE60101159 D1 DE 60101159D1 DE 60101159 T DE60101159 T DE 60101159T DE 60101159 T DE60101159 T DE 60101159T DE 60101159 D1 DE60101159 D1 DE 60101159D1
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Germany
Prior art keywords
stack
chip
manufacturing
case
disc level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60101159T
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English (en)
Other versions
DE60101159T2 (de
Inventor
M Lam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
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Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Application granted granted Critical
Publication of DE60101159D1 publication Critical patent/DE60101159D1/de
Publication of DE60101159T2 publication Critical patent/DE60101159T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60101159T 2000-03-09 2001-01-10 Herstellungsmethode eines stapelchip-ic-gehäuses auf scheibenebene Expired - Fee Related DE60101159T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/521,299 US6344401B1 (en) 2000-03-09 2000-03-09 Method of forming a stacked-die integrated circuit chip package on a water level
US521299 2000-03-09
PCT/US2001/000828 WO2001067511A2 (en) 2000-03-09 2001-01-10 Method of forming a stacked-die integrated circuit chip package on a wafer level

Publications (2)

Publication Number Publication Date
DE60101159D1 true DE60101159D1 (de) 2003-12-11
DE60101159T2 DE60101159T2 (de) 2004-08-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE60101159T Expired - Fee Related DE60101159T2 (de) 2000-03-09 2001-01-10 Herstellungsmethode eines stapelchip-ic-gehäuses auf scheibenebene

Country Status (12)

Country Link
US (1) US6344401B1 (de)
EP (1) EP1269538B1 (de)
JP (1) JP2003526922A (de)
KR (1) KR20020086612A (de)
CN (1) CN1194408C (de)
CA (1) CA2400805A1 (de)
DE (1) DE60101159T2 (de)
HK (1) HK1052579A1 (de)
MY (1) MY134235A (de)
NO (1) NO20023891D0 (de)
TW (1) TW484214B (de)
WO (1) WO2001067511A2 (de)

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6511901B1 (en) * 1999-11-05 2003-01-28 Atmel Corporation Metal redistribution layer having solderable pads and wire bondable pads
JP4403631B2 (ja) * 2000-04-24 2010-01-27 ソニー株式会社 チップ状電子部品の製造方法、並びにその製造に用いる擬似ウエーハの製造方法
JP2001313350A (ja) * 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
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CN1194408C (zh) 2005-03-23
KR20020086612A (ko) 2002-11-18
CN1416594A (zh) 2003-05-07
WO2001067511A2 (en) 2001-09-13
TW484214B (en) 2002-04-21
CA2400805A1 (en) 2001-09-13
US6344401B1 (en) 2002-02-05
HK1052579A1 (en) 2003-09-19
JP2003526922A (ja) 2003-09-09
NO20023891L (no) 2002-08-16
NO20023891D0 (no) 2002-08-16
EP1269538B1 (de) 2003-11-05
MY134235A (en) 2007-11-30

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