DE60210871D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE60210871D1
DE60210871D1 DE60210871T DE60210871T DE60210871D1 DE 60210871 D1 DE60210871 D1 DE 60210871D1 DE 60210871 T DE60210871 T DE 60210871T DE 60210871 T DE60210871 T DE 60210871T DE 60210871 D1 DE60210871 D1 DE 60210871D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60210871T
Other languages
English (en)
Other versions
DE60210871T2 (de
Inventor
Koichi Kamiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE60210871D1 publication Critical patent/DE60210871D1/de
Publication of DE60210871T2 publication Critical patent/DE60210871T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
DE60210871T 2001-06-26 2002-06-26 Halbleiterspeicheranordnung Expired - Lifetime DE60210871T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001192713 2001-06-26
JP2001192713A JP2003007071A (ja) 2001-06-26 2001-06-26 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE60210871D1 true DE60210871D1 (de) 2006-06-01
DE60210871T2 DE60210871T2 (de) 2006-11-16

Family

ID=19031127

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60210871T Expired - Lifetime DE60210871T2 (de) 2001-06-26 2002-06-26 Halbleiterspeicheranordnung

Country Status (6)

Country Link
US (1) US6731549B2 (de)
EP (1) EP1278198B1 (de)
JP (1) JP2003007071A (de)
KR (1) KR100523507B1 (de)
DE (1) DE60210871T2 (de)
TW (1) TW561481B (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007071A (ja) * 2001-06-26 2003-01-10 Sharp Corp 半導体メモリ装置
KR100521759B1 (ko) * 2003-03-27 2005-10-17 학교법인 인하학원 모서리 감지 종료 회로 및 이를 이용한 고속의 비동기파이프라인 회로
JP4667190B2 (ja) * 2005-09-29 2011-04-06 パナソニック株式会社 レベル変換回路
JP5529661B2 (ja) * 2010-07-23 2014-06-25 ラピスセミコンダクタ株式会社 半導体メモリ
KR102491689B1 (ko) * 2016-03-03 2023-01-26 에스케이하이닉스 주식회사 반도체장치
CN106297867B (zh) * 2016-08-09 2019-05-28 武汉新芯集成电路制造有限公司 一种地址匹配电路
US10074493B2 (en) * 2016-11-21 2018-09-11 Aeroflex Colorado Springs Inc. Radiation-hardened break before make circuit
CN113640656B (zh) * 2021-07-30 2024-04-09 深圳速跃芯仪科技有限公司 基于延时的数字测试码型生成方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5228003A (en) 1988-04-15 1993-07-13 Seiko Epson Corporation Semiconductor memory
US5124584A (en) 1990-10-22 1992-06-23 Sgs-Thomson Microelectronics, Inc. Address buffer circuit with transition-based latching
US5493537A (en) 1994-02-28 1996-02-20 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with edge transition detection pulse disable
KR0177763B1 (ko) * 1995-11-13 1999-04-15 김광호 비트라인 프리차아지회로
JPH09306184A (ja) * 1996-05-14 1997-11-28 Asahi Kasei Micro Syst Kk 半導体回路
KR100239885B1 (ko) * 1997-01-13 2000-01-15 윤종용 Sram 장치의 비트라인 프리챠지 회로
US5940337A (en) 1997-10-23 1999-08-17 Integrated Silicon Solution, Inc. Method and apparatus for controlling memory address hold time
US5986970A (en) 1998-06-29 1999-11-16 Cypress Semiconductor Corp. Method, architecture and circuit for writing to a memory
KR100287542B1 (ko) * 1998-11-26 2001-04-16 윤종용 웨이브 파이프라인 스킴을 구비한 동기형 반도체 메모리 장치및 그것의 데이터 패스 제어 방법
JP2000268576A (ja) * 1999-03-16 2000-09-29 Toshiba Microelectronics Corp 半導体記憶装置
US6590822B2 (en) * 2001-05-07 2003-07-08 Samsung Electronics Co., Ltd. System and method for performing partial array self-refresh operation in a semiconductor memory device
JP2003007071A (ja) * 2001-06-26 2003-01-10 Sharp Corp 半導体メモリ装置

Also Published As

Publication number Publication date
EP1278198A3 (de) 2003-11-12
US6731549B2 (en) 2004-05-04
EP1278198A2 (de) 2003-01-22
US20020196674A1 (en) 2002-12-26
TW561481B (en) 2003-11-11
JP2003007071A (ja) 2003-01-10
KR100523507B1 (ko) 2005-10-24
DE60210871T2 (de) 2006-11-16
EP1278198B1 (de) 2006-04-26
KR20030011244A (ko) 2003-02-07

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Legal Events

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8364 No opposition during term of opposition