TW484214B - Method of forming a stacked-die integrated circuit chip package on a wafer level - Google Patents

Method of forming a stacked-die integrated circuit chip package on a wafer level Download PDF

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Publication number
TW484214B
TW484214B TW090104987A TW90104987A TW484214B TW 484214 B TW484214 B TW 484214B TW 090104987 A TW090104987 A TW 090104987A TW 90104987 A TW90104987 A TW 90104987A TW 484214 B TW484214 B TW 484214B
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Taiwan
Prior art keywords
wafer
die
bonding pads
individual
grains
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TW090104987A
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English (en)
Inventor
Ken M Lam
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Atmel Corp
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Publication of TW484214B publication Critical patent/TW484214B/zh

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Description

Λ、贫明說明（1) 【技術領域 本發明係 豐晶粒積體 【背景技術 晶粒封裝 損壞，而且 接積體電路 接連接進入 晶片積體電 接置放多晶 接及低電容： 封裝密度及 化，而且減 斷絕。另外 電路板互連 晶片進入同 電路積體電 域。 關於積體電路晶粒封 電路晶片之私壯一 尤其係關於晶圓級堆 71 <封裝方法。 係用以 用以提 保護積 供—個 曰曰片或晶粒於 一個電子產品 封裝有 晶片及 其供給 能。多 基板上 免基板 電容及 封裝， 之覆蓋 IIΓ路ί片，使其不受到污染和 _ 的實質的電氣引線系統供連 。個=在印刷電路板之上或者直 k ί單一晶片載體上提供一個多 二的優點。經由在一基板上直 a電力線之間提供低電感連 曰固很密集的互連網路，可增進 :安晶片至晶片間隔最低 上較二曰曰片之間的電感及電容 雷^乍且較短的電線具有比印刷 以2堆®多重的相同積體電路 更^加記憶體而沒有增加一個 m，或者電路板上所佔有之區 、在先前技術中，通常為構成多曰 或一組的晶片裝配。其餘的人已曰曰月封裝之各個別的一對 封裝是較有利的，即，在各個別了 f能夠在晶圓級形成1C 後，但在晶圓被切割成個別晶片之=粒已形成在這晶圓 量生產晶片封裝及一些晶圓^裝，珂。這允許更容易地大 陣袼式，一次完成全部製造及^蚪在晶圓上被安排成一矩
。可減少封裝及測試IC 晶片之製程的時間及 大部分之先前技術的晶阊S 士 晶粒之封裝。涉及多曰曰9圓、、及封裝計劃涉及單一積體電路 數個晶圓而企圖形成丰曾粒之其他封裝计劃則經由堆疊複 第5, 952, 72 5號揭露—^體裝置。例如，Bal 1之美國專利 一上晶圓及一下晶圓，发增加電路密度之方法，經由堆疊 中有裝配的電路。上^其f在其個別面表面上之特定區域 層黏接劑塗敷在下晶^圓^背對背地附著於下晶圓，以一 一各晶圓上之相配的^:背面。這些晶圓被對齊使得在每 身則附著到一黏著劑薄f垂直對齊。附著的一對晶圓本 一孤日问π、丄 ’、騰使晶圓於切粒時不能叙。益从 一對日日固可被切粒成個別晶不此動附者的 圓部份。Cronin等人之美車子或匕3超過一晶粒對之晶 疊的三維裝置，其之利第5’δ72,〇25號揭露一堆 裝置之另一選擇。晶片區二= 晶圓以作為堆疊個別 區域被一絕緣體充滿的溝渠^ ^些晶圓上，而各晶片 域一起被堆疊對齊且經由芦界 這些晶圓跟著與晶粒區 之後，晶粒堆疊經由蝕刻7 ^加在一起。在層壓晶圓堆疊 諸方法之一問題係，諸如^ ^或其他製程而被分離。 被互相對齊，附著在一起，然/之方去，其中，整個晶圓 證所有的個別晶粒對皆是"好、、彳^切成個別晶粒對，但不保 齊諸晶圓時，一個好的晶粒可2能正常。例如，於對 個功能不正常之晶粒對齊。一 g = 一個壞的"晶粒或者一 壞的晶粒之組合的堆疊晶粒封】^ —個好的晶粒及一個 晶粒封裝而被拋棄。最後導致、^ $後會導致一個壞的堆疊 K費許多好的晶粒。
本發明之__ 裝的方法，复：目的係提供—種形成堆疊晶粒積體電敗 生-個積體電次晶圓上之所有Γ; 的覆蓋區。 士衣/、/、有堆疊晶粒封裝用之最小飞產 % 4 口J 能 本發明之另— y 粒封裝的方法—=的係提供一種形成堆疊晶粒積俨雷 壯 其導致只有好的曰抑分h τ償版電路晶 ，好的晶粒之浪費最低化曰拉被封裂成堆疊晶粒封 【發明概述】 本發明之上述目的可藉—插曰门 允許一次封裝在—晶圓上之^曰囫級封裝方法而完成，其 堆疊的雙/多重曰' 的半導體晶粒，及產；Ψ八 ^ _ 里日日粒積體電路封驻 π也丨 汉座生一 ^晶片尺寸封裝，其具有堆聂' °衣造的封裝是一個 覆蓋區。⑨這方法中，具有二：立封裝用之最小可能的 圓的製程可經過-個金屬重分：：，較小尺寸的晶粒之晶 圓被鋸成個別晶粒尺寸球柵陣列=，然後附著焊球。晶 大尺寸晶粒之晶圓上，一個::陶封裝。在這具有較 各晶粒地點位置之前方，係意圖付f黏著劑材料被沉積在 裝。BGA晶粒封裝之被放置在付著一個晶粒尺寸BGA封 線結合操作從晶粒尺寸BGA封^ =蜊材料上而保存。一個 上之底部晶粒的電路。一種塗声接堵汛號到形成在晶圓 被配置在晶圓上以蓋著線結合s $料，諸如環氧基樹脂， 完成的堆疊晶粒，還是呈晶圓矩陳=件跟著被保存。這 之最終測試或平行測試。跟著，$ =式，有利於容易索引 成為個別的堆疊晶粒IC封,士堆®的晶粒晶圓被單獨化 _ 、。本發明的方法允許具有相同 __
\\326\2d-\90>05\90104987.ntH 484214 五、發明說明（4) 或不同功能之晶粒被組合成一個單一 【實施本發明的最佳模式】 衣。 矽i:】1的材：'第一矽晶圓21及-第二矽晶圓u。雖然 ；/疋/ i的材料，也可使用其他 各有複數個微電 電二2 ::圓21’11 或晶粒之矩陣。如圖丨所示，在第Λ路圓^排成個別晶片 是大於在第二曰圓η，夕θ 日日固21上之晶粒24, 25 ^ ^ # ^ , ；； ^ ^ 5 ^ 晶圓矩陣格式•，晶片可被測試，以：;曰片:久：：於 確，及那個晶片功能不正石$。 、疋㈣Β曰片功此正 參考圖2，第一曰mi1 士、— 表心。於⑽安排環繞上 被使用為各個別晶粒用之連接點，^1延些結合墊16可 可經歷-金屬重分配製程。全屬重if:011之上表面19 接到線結合墊，铁後重刀配衣程仿造金屬跡連 内之焊墊位置:、女見疋路線將這些跡連到在各晶粒 Γ 用晶粒材料之良好黏 金應是使用紹或黃全線 貝方；線結合墊連接點，冶 適合於可靠可焊。在焊塾位置之冶金應是 形：ΪΓ型：屬一重金分屬配 ^,0 9/434, 7 π ；；ΐ：ΠΪ；^
ItA) ^ 曰ms b ，考圖3，一被動層41被形成於 00 二金屬層結構4 Μ皮形成於結合墊1 6及被 m 第8頁 \\326\2d-\90-05\90104987.ptd 484214 五、發明說明（5) 動層41上。二金屬層結構4〇包括一紹層43，一鎳層45及一 銅層47。一第二被動層49然後形成於三金屬層4〇上。組件 被#刻使得一銅材料之焊墊5 2及一鋁材料製造之線結合墊 60被形成。焊球5〇然後可被放置在焊墊52上。焊球5〇可被 放置在焊墊5 2上經過一機械移轉的預先形成的焊球。此 外’可以網印或油印焊接劑糊形成焊球5 〇。焊接劑然後流 回以形成封裝的焊球。可以想要之任何圖形應用焊球5 〇， 例如’在全部的晶圓表面之上之均勻的完整矩陣。 於這點，第二晶圓11被切粒成個別晶片。參考圖4及圖 1，各晶粒1 5的尺寸是足夠的小，使得晶粒丨5可套入第一 晶圓21上之空間26，當晶粒15被堆疊在晶圓21上時，使得 晶粒1 5不會侵入第一晶圓2 1之晶粒2 4，2 5之結合墊2 3。如 圖4所示，複數個焊球50及線結合墊6〇被安排在晶粒15的 上表面1 2上。 苓考圖5，不第一晶圓2 1的一部分5 - 5及鋁結合墊2 3被置 在晶圓2 1的上表面上。如上所述，晶圓2丨被安排成一個別 晶粒24, 2 5的矩陣。參考圖6，來自第二晶圓的晶粒14，15 被安排在一晶圓2 1的頂表面上。呈一球柵陣列格式之晶粒 1 4，1 5可使用一檢取及放置機器而被將其放置在晶圓2工 上，以提供準確放置各頂晶粒球柵陣列在底晶圓2 1上。晶 粒1 4，1 5應被安排使得晶圓2 1的每一晶粒2 4，2 5上之線結合 墊2 3露出。附著晶粒1 4，1 5到晶圓2 1，一黏著性材料1 8， 諸如環氧基樹脂或熱塑膠，以糊形成或預先形成薄膜，置 於晶圓的頂表面21上。可使用自動糊分配裝備沉積一'糊材
\\326\2d-\90-05\90104987.ptd 第9頁 484214 五、發明說明（6) 料，或假如這黏接劑是呈一預先形成，可使用檢取及放置 裝備。晶粒14, 15的背面放置在黏著性材料18上。晶粒結 合黏接劑然後被保存。
參考圖7，然後指引一線結合操作以自每一頂部晶粒連 接這些成號到在晶圓2 1上之每一底部晶粒。例如，為連接 上晶粒15及下晶粒25，自頂部晶粒15之線結合墊6〇連接黃 金線結合引線7 0到晶圓2 1上之底部晶粒2 5的線結合墊2 3。 此使用k準線結合技術完成。然後，參考圖8，使用一包 覆材料’諸如環氧基樹脂，以包覆線結合引線7 〇。重要的 疋將包覆材料的合成高度最低化，用以將垂直空氣的使用 最低化。然後保存這包覆材料8 〇。於這點，封裝測試可實 行於Μ粒矩陣形式。參考圖g，一頂端晶粒丨5已放置於晶 圓2 1的每個晶粒25的頂部。使用諸線結合引線7〇連接上晶 粒15的結合墊16到下晶粒25的結合墊23。包覆材料8〇包覆 所有之線結合引線7〇，但是不包覆焊球5〇及晶粒的頂表面
參考圖1 0，第一晶圓然後被單獨化，或切粒，成為個 的晶片晶粒封裝91。單獨化的普通技巧為使用具有鑽石 樹脂般的晶圓錯子。再次，在晶圓被單獨化成為個 片晶粒封裝9 1之後，也可實行封裝測試。本發明之b 堆豐晶粒BGA封裝91接著可以使用於先前技術的bga封 樣的方式被女裝在一最後使用者的印刷電路板上。^ =之堆疊晶粒BGA封裝包含較小晶粒15及較大晶粒25且= 如較大晶粒25般之相同覆蓋區，由於這種κ封裝，因/
484214 五、發明說明（7) 不需要額外的空 皆被單獨地放置 中二晶圓是堆疊 一晶圓的已知好 間。此外，因為來自第二晶圓的每一晶粒 在第一晶圓上，相反於先前技術方法，其 在一起’弟"一晶圓的已知好的晶粒可與弟 的晶粒排成一線以將任何好的晶粒之浪費 最低化。此外，本發明的方法也可重複於多重晶粒以堆疊 超過二晶粒於一單一 I C封裝，且因此，增加I C封裝的記憶 而沒有增加一印刷電路板上所需的空間數量。 【元件編號之說明】 11 弟·一碎晶圓 14, 15 晶粒 16 鋁結合墊 18 黏著性材料 19 上表面 21 碎晶圓 23 鋁結合墊 24, 25 晶粒 26 空間 40 三金屬層結構 41 被動層 43 鋁層 45 鎳層 47 銅層 50 焊球 52 焊墊
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\\326\2d-\90-05\90104987.ptd 第12頁 484214 圖式簡單說明 曰曰 圖1是第一及第二矽晶圓的透視圖，各晶圓有複數個 粒形成於頂表面。 圖2及3是圖1所示之第二晶圓1 1的部分2 - 2之橫剖面圖， 况明苐^一晶圓的金屬重分配製程。 圖4是圖1所示之第二晶圓在附著焊球之後，其中之一晶 粒的透視圖。 圖5 - 8是圖1所示之第一晶圓的部分5 - 5之橫剖面圖， 顯示使用本發明的方法於形成一 I C封裝所用之各種製程步 驟。 圖9是在完成圖5 - 8之製程步驟之後，圖1的第一晶圓之 俯視圖。 圖1 0是本發明的方法所形成之完成I C封裝之橫剖面圖。
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Claims (1)

  1. 六、申請專利範圍 含· ’重曰曰圓級堆疊晶粒積體電路晶片之封裝方法，包 半導體晶圓和-第二半導體晶圓，每 包括複數個晶粒，第—日圓的耝日日圆，母一晶圓 複::Ϊ::互連到第二晶圓的複數個晶粒的第-表面之 將第二晶圓切粒成為複數個個別晶粒， 粒之個別晶粒到第一晶圓，㊣中-個個別晶 被置放附著到第一晶圓的第一表面，在第一曰 上形成複數個封裝結構， 弟日日圓 連^個別晶粒的複數個結合墊到第一 的禝數個結合墊，及 ^夂妖w日日粒 裝將弟—晶κ切粒成為複數個個制堆疊晶粒積體電路封 2.如申請專利範圍第丨項之方法，更包含， Ζ ΐ=:晶圓的複數個晶粒的第-表面的複數：Λ 3之步咏之則’形成一金屬重分配層在第二晶 ：= 面以形成一複數個線結合墊及互連墊。 表 3·如申請專利範圍第2項之方法，其 到第二晶圓的金屬重分配層上之互連墊。 白附著 4·如申請專利範圍第2項之方法，其中，個 複數個線結合墊皆連接到第一晶圓的複數個結 484214 六、申請專利範圍 5.如申請專利範圍第1項之方法，其中，連接個別晶粒 的複數個線結合墊到第一晶圓的複數個結合墊是以複數個 結合引線完成的。 6 ·如申請專利範圍第5項之方法，更包含，在連接個別 晶粒的複數個線結合墊到第一晶圓的複數個結合墊的步驟 之後，塗一包覆材料於複數個結合引線之上。 7. 如申請專利範圍第6項之方法，其中，包覆材料是環 氧基樹脂。 8. 如申請專利範圍第1項之方法，其中，更包含，在連 接個別晶粒的複數個線結合墊到第一晶圓的複數個線結合 墊的步驟之後，在第一晶圓上測試封裝結構。 9. 如申請專利範圍第1項之方法，其中，複數個互連是 複數個焊球。 1 0.如申請專利範圍第1項之方法，其中，個別晶粒皆以 一黏著性材料附著到第一晶圓。 11.，一種晶圓級堆雙晶粒積體電路晶片之封裝方法，包 含： 提供一第一半導體晶圓和一第二半導體晶圓，每一晶圓 包括複數個晶粒，弟二晶圓的複數個晶粒的尺寸小於弟一 晶圓的複數個晶粒，每一複數個晶粒具有複數個結合墊置 於其第一表面， 形成一金屬重分配層於第二晶圓的第一表面，以形成複 數個線結合墊及互連墊， 附著複數個互連到第二晶圓之金屬重分配層的互連墊，
    \\326\2d-\90-05\90104987.ptd 第15頁 484214 六、申請專利範圍 將第二晶圓切粒成為複數個個別晶粒， 附著個別晶粒到第一晶圓，其中一個個別晶粒的背面被 置放附著到第一晶圓的第一表面，在第一晶圓上形成複數 個封裝結構， 連接個別晶粒的複數個線結合墊到第一晶圓的複數個結 合塾，及 將弟'^晶圓切粒成為複數個個別的堆豐晶粒積體電路封 裝。 1 2.如申請專利範圍第1 1項之方法，其中，連接個別晶 粒的複數個線結合墊到第一晶圓的複數個結合墊是以複數 個結合引線完成的。 1 3.如申請專利範圍第1 2項之方法，更包含，在連接個 別晶粒的複數個線結合墊到第一晶圓的複數個結合墊的步 驟之後，塗一包覆材料於複數個結合引線之上。 1 4.如申請專利範圍第1 3項之方法，其中，包覆材料是 環氧基樹脂。 1 5.如申請專利範圍第1 1項之方法，其中，更包含，在 連接個別晶粒的複數個線結合墊到第一晶圓的複數個線結 合墊的步驟之後，在第一晶圓上測試封裝結構。 1 6.如申請專利範圍第1 1項之方法，其中，複數個互連 是複數個焊球。 1 7.如申請專利範圍第1 1項之方法，其中，個別晶粒皆 以一黏著性材料附著到第一晶圓。 18. 種晶圓級堆®晶粒積體電路晶片之封裝方法’包
    \\326\2d-\90-05\90104987.ptd 第16頁 484214 六、申請專利範圍 含： 提供一第一半導體晶圓和一第二半導體晶圓，每一晶圓 包括複數個晶粒，第二晶圓的複數個晶粒的尺寸小於第一 晶圓的複數個晶粒，每一複數個晶粒具有複數個結合墊置 於其第一表面， 形成一金屬重分配層於第二晶圓的第一表面，以形成複 數個線結合墊及互連墊， 附著複數個錫球到第二晶圓之金屬重分配層的互連墊， 將第二晶圓切粒成為複數個個別晶粒， 附著個別晶粒到第一晶圓，其中一個個別晶粒的背面被 置放附著到第一晶圓的第一表面，在第一晶圓上形成複數 個封裝結構， 使用複數個結合引線以連接個別晶粒的複數個線結合墊 到第一晶圓的複數個結合墊， 塗一包覆材料於複數個結合引線之上， 測試在該第一晶圓上之封裝結構，及 將第一晶圓切粒成為複數個個別堆疊晶粒積體電路晶片 封裝。
    \\326\2d-\90-05\90104987.ptd 第17頁
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