IT1318979B1 - Architettura di memoria a semiconduttore - Google Patents

Architettura di memoria a semiconduttore

Info

Publication number
IT1318979B1
IT1318979B1 IT2000MI002165A ITMI20002165A IT1318979B1 IT 1318979 B1 IT1318979 B1 IT 1318979B1 IT 2000MI002165 A IT2000MI002165 A IT 2000MI002165A IT MI20002165 A ITMI20002165 A IT MI20002165A IT 1318979 B1 IT1318979 B1 IT 1318979B1
Authority
IT
Italy
Prior art keywords
semiconductor memory
memory architecture
architecture
semiconductor
memory
Prior art date
Application number
IT2000MI002165A
Other languages
English (en)
Inventor
Luigi Pascucci
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000MI002165A priority Critical patent/IT1318979B1/it
Publication of ITMI20002165A0 publication Critical patent/ITMI20002165A0/it
Priority to US09/972,769 priority patent/US6580637B2/en
Publication of ITMI20002165A1 publication Critical patent/ITMI20002165A1/it
Application granted granted Critical
Publication of IT1318979B1 publication Critical patent/IT1318979B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
IT2000MI002165A 2000-10-06 2000-10-06 Architettura di memoria a semiconduttore IT1318979B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000MI002165A IT1318979B1 (it) 2000-10-06 2000-10-06 Architettura di memoria a semiconduttore
US09/972,769 US6580637B2 (en) 2000-10-06 2001-10-05 Semiconductor memory architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000MI002165A IT1318979B1 (it) 2000-10-06 2000-10-06 Architettura di memoria a semiconduttore

Publications (3)

Publication Number Publication Date
ITMI20002165A0 ITMI20002165A0 (it) 2000-10-06
ITMI20002165A1 ITMI20002165A1 (it) 2002-04-06
IT1318979B1 true IT1318979B1 (it) 2003-09-19

Family

ID=11445922

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000MI002165A IT1318979B1 (it) 2000-10-06 2000-10-06 Architettura di memoria a semiconduttore

Country Status (2)

Country Link
US (1) US6580637B2 (it)
IT (1) IT1318979B1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4050548B2 (ja) * 2002-04-18 2008-02-20 株式会社ルネサステクノロジ 半導体記憶装置
ITRM20020369A1 (it) * 2002-07-09 2004-01-09 Micron Technology Inc Architettura a burst per memoria a doppio bus.
US7177212B2 (en) * 2004-01-23 2007-02-13 Agere Systems Inc. Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase
JP2007011872A (ja) * 2005-07-01 2007-01-18 Toshiba Corp メモリカードとその制御方法
TWI348617B (en) * 2007-08-09 2011-09-11 Skymedi Corp Non-volatile memory system and method for reading data therefrom

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3789173B2 (ja) * 1996-07-22 2006-06-21 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及び半導体記憶装置のアクセス方法
US6233199B1 (en) * 1999-02-26 2001-05-15 Micron Technology, Inc. Full page increment/decrement burst for DDR SDRAM/SGRAM
US6259627B1 (en) * 2000-01-27 2001-07-10 Multi Level Memory Technology Read and write operations using constant row line voltage and variable column line load

Also Published As

Publication number Publication date
ITMI20002165A1 (it) 2002-04-06
US6580637B2 (en) 2003-06-17
US20020067640A1 (en) 2002-06-06
ITMI20002165A0 (it) 2000-10-06

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