DE60042246D1 - In-situ nachätzungs prozess zur entfernung von pho - Google Patents

In-situ nachätzungs prozess zur entfernung von pho

Info

Publication number
DE60042246D1
DE60042246D1 DE60042246T DE60042246T DE60042246D1 DE 60042246 D1 DE60042246 D1 DE 60042246D1 DE 60042246 T DE60042246 T DE 60042246T DE 60042246 T DE60042246 T DE 60042246T DE 60042246 D1 DE60042246 D1 DE 60042246D1
Authority
DE
Germany
Prior art keywords
etch
pho
wafer
renewal process
oxygen plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60042246T
Other languages
German (de)
English (en)
Inventor
Robert J O'donnell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Application granted granted Critical
Publication of DE60042246D1 publication Critical patent/DE60042246D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02054—Cleaning before device manufacture, i.e. Begin-Of-Line process combining dry and wet cleaning steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Removal Of Specific Substances (AREA)
DE60042246T 1999-12-27 2000-12-21 In-situ nachätzungs prozess zur entfernung von pho Expired - Lifetime DE60042246D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/472,757 US6852636B1 (en) 1999-12-27 1999-12-27 Insitu post etch process to remove remaining photoresist and residual sidewall passivation
PCT/US2000/035165 WO2001048808A1 (en) 1999-12-27 2000-12-21 An insitu post etch process to remove remaining photoresist and residual sidewall passivation

Publications (1)

Publication Number Publication Date
DE60042246D1 true DE60042246D1 (de) 2009-07-02

Family

ID=23876824

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60042246T Expired - Lifetime DE60042246D1 (de) 1999-12-27 2000-12-21 In-situ nachätzungs prozess zur entfernung von pho

Country Status (10)

Country Link
US (1) US6852636B1 (enExample)
EP (1) EP1243023B1 (enExample)
JP (2) JP2003518768A (enExample)
KR (1) KR100794538B1 (enExample)
CN (1) CN1210773C (enExample)
AT (1) ATE431964T1 (enExample)
AU (1) AU2737301A (enExample)
DE (1) DE60042246D1 (enExample)
TW (1) TW471060B (enExample)
WO (1) WO2001048808A1 (enExample)

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EP1320128B1 (en) * 2001-12-17 2006-05-03 AMI Semiconductor Belgium BVBA Method for making interconnect structures
US6943039B2 (en) * 2003-02-11 2005-09-13 Applied Materials Inc. Method of etching ferroelectric layers
CN100444025C (zh) * 2004-07-12 2008-12-17 北京北方微电子基地设备工艺研究中心有限责任公司 光刻胶修整方法
US7597816B2 (en) * 2004-09-03 2009-10-06 Lam Research Corporation Wafer bevel polymer removal
US7413993B2 (en) * 2004-11-22 2008-08-19 Infineon Technologies Ag Process for removing a residue from a metal structure on a semiconductor substrate
JP4518986B2 (ja) * 2005-03-17 2010-08-04 東京エレクトロン株式会社 大気搬送室、被処理体の処理後搬送方法、プログラム及び記憶媒体
US20060246720A1 (en) * 2005-04-28 2006-11-02 Chii-Ming Wu Method to improve thermal stability of silicides with additives
US20070032081A1 (en) 2005-08-08 2007-02-08 Jeremy Chang Edge ring assembly with dielectric spacer ring
US7479457B2 (en) * 2005-09-08 2009-01-20 Lam Research Corporation Gas mixture for removing photoresist and post etch residue from low-k dielectric material and method of use thereof
US20070227555A1 (en) * 2006-04-04 2007-10-04 Johnson Michael R Method to manipulate post metal etch/side wall residue
JP2014212310A (ja) * 2013-04-02 2014-11-13 東京エレクトロン株式会社 半導体デバイスの製造方法及び製造装置
JP6844083B2 (ja) * 2015-05-27 2021-03-17 サムコ株式会社 アフターコロージョン抑制処理方法
CN107464750B (zh) * 2017-08-23 2019-12-13 成都海威华芯科技有限公司 一种去除光刻胶底膜的工艺方法
US11749532B2 (en) 2021-05-04 2023-09-05 Applied Materials, Inc. Methods and apparatus for processing a substrate
KR20240086974A (ko) * 2022-12-12 2024-06-19 피에스케이 주식회사 기판 처리 장치 및 기판 처리 방법
US20250118532A1 (en) * 2023-10-09 2025-04-10 Tokyo Electron Limited System and method for plasma processing

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US4804431A (en) 1987-11-03 1989-02-14 Aaron Ribner Microwave plasma etching machine and method of etching
JP2831646B2 (ja) * 1988-03-25 1998-12-02 株式会社東芝 半導体装置の製造方法
US4985113A (en) 1989-03-10 1991-01-15 Hitachi, Ltd. Sample treating method and apparatus
US5186718A (en) * 1989-05-19 1993-02-16 Applied Materials, Inc. Staged-vacuum wafer processing system and method
JPH0341728A (ja) * 1989-07-07 1991-02-22 Fujitsu Ltd 半導体装置の製造方法
DE69033663T2 (de) 1989-08-28 2001-06-21 Hitachi, Ltd. Verfahren zur Behandlung eines Aluminium enthaltenden Musters
US5198634A (en) 1990-05-21 1993-03-30 Mattson Brad S Plasma contamination removal process
JP2998173B2 (ja) * 1990-06-01 2000-01-11 松下電器産業株式会社 Ａｌエッチング方法
WO1992000601A1 (fr) 1990-06-27 1992-01-09 Fujitsu Limited Procede de fabrication d'un circuit integre a semi-conducteurs et appareil de fabrication correspondant
US5174856A (en) 1991-08-26 1992-12-29 Applied Materials, Inc. Method for removal of photoresist over metal which also removes or inactivates corrosion-forming materials remaining from previous metal etch
JPH05275325A (ja) * 1992-03-26 1993-10-22 Fujitsu Ltd 半導体装置の製造方法
US5462892A (en) 1992-06-22 1995-10-31 Vlsi Technology, Inc. Semiconductor processing method for preventing corrosion of metal film connections
US5931721A (en) 1994-11-07 1999-08-03 Sumitomo Heavy Industries, Ltd. Aerosol surface processing
JPH08213366A (ja) * 1995-02-07 1996-08-20 Hitachi Ltd パターン形成方法およびパターン形成装置、ならびに半導体集積回路装置の製造方法および半導体製造装置
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WO1997011482A2 (en) 1995-09-05 1997-03-27 Lsi Logic Corporation Removal of halogens and photoresist from wafers
US5573961A (en) 1995-11-09 1996-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Method of making a body contact for a MOSFET device fabricated in an SOI layer
US5780359A (en) * 1995-12-11 1998-07-14 Applied Materials, Inc. Polymer removal from top surfaces and sidewalls of a semiconductor wafer
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US5712207A (en) 1996-02-29 1998-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Profile improvement of a metal interconnect structure on a tungsten plug
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US5908319A (en) 1996-04-24 1999-06-01 Ulvac Technologies, Inc. Cleaning and stripping of photoresist from surfaces of semiconductor wafers
US5882489A (en) 1996-04-26 1999-03-16 Ulvac Technologies, Inc. Processes for cleaning and stripping photoresist from surfaces of semiconductor wafers
US5776832A (en) 1996-07-17 1998-07-07 Taiwan Semiconductor Manufacturing Company Ltd. Anti-corrosion etch process for etching metal interconnections extending over and within contact openings
US5779929A (en) 1996-10-07 1998-07-14 Lucent Technologies Inc. Thin film metallization for barium nanotitanate substrates
US5744395A (en) 1996-10-16 1998-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Low resistance, self-aligned, titanium silicide structures, using a single rapid thermal anneal procedure
US5795831A (en) 1996-10-16 1998-08-18 Ulvac Technologies, Inc. Cold processes for cleaning and stripping photoresist from surfaces of semiconductor wafers
US5899716A (en) 1997-05-19 1999-05-04 Vanguard International Semiconductor Corporation Oxygen ion implantation procedure to increase the surface area of an STC structure
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US5846884A (en) 1997-06-20 1998-12-08 Siemens Aktiengesellschaft Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing
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Also Published As

Publication number Publication date
AU2737301A (en) 2001-07-09
TW471060B (en) 2002-01-01
CN1210773C (zh) 2005-07-13
CN1434978A (zh) 2003-08-06
WO2001048808A1 (en) 2001-07-05
KR20020081234A (ko) 2002-10-26
ATE431964T1 (de) 2009-06-15
US6852636B1 (en) 2005-02-08
KR100794538B1 (ko) 2008-01-17
EP1243023A1 (en) 2002-09-25
EP1243023B1 (en) 2009-05-20
JP2003518768A (ja) 2003-06-10
JP2012023385A (ja) 2012-02-02

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Legal Events

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