KR100794538B1 - 잔류 포토레지스트 및 잔여 측벽 패시베이션을 제거하는인시츄 포스트 에칭방법 - Google Patents

잔류 포토레지스트 및 잔여 측벽 패시베이션을 제거하는인시츄 포스트 에칭방법 Download PDF

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Publication number
KR100794538B1
KR100794538B1 KR1020027008271A KR20027008271A KR100794538B1 KR 100794538 B1 KR100794538 B1 KR 100794538B1 KR 1020027008271 A KR1020027008271 A KR 1020027008271A KR 20027008271 A KR20027008271 A KR 20027008271A KR 100794538 B1 KR100794538 B1 KR 100794538B1
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South Korea
Prior art keywords
etching
substrate
chamber
etch
containing layer
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Expired - Fee Related
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KR1020027008271A
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English (en)
Korean (ko)
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KR20020081234A (ko
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로버트 제이. 오도넬
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램 리서치 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02054—Cleaning before device manufacture, i.e. Begin-Of-Line process combining dry and wet cleaning steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Removal Of Specific Substances (AREA)
KR1020027008271A 1999-12-27 2000-12-21 잔류 포토레지스트 및 잔여 측벽 패시베이션을 제거하는인시츄 포스트 에칭방법 Expired - Fee Related KR100794538B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/472,757 US6852636B1 (en) 1999-12-27 1999-12-27 Insitu post etch process to remove remaining photoresist and residual sidewall passivation
US09/472,757 1999-12-27

Publications (2)

Publication Number Publication Date
KR20020081234A KR20020081234A (ko) 2002-10-26
KR100794538B1 true KR100794538B1 (ko) 2008-01-17

Family

ID=23876824

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020027008271A Expired - Fee Related KR100794538B1 (ko) 1999-12-27 2000-12-21 잔류 포토레지스트 및 잔여 측벽 패시베이션을 제거하는인시츄 포스트 에칭방법

Country Status (10)

Country Link
US (1) US6852636B1 (enExample)
EP (1) EP1243023B1 (enExample)
JP (2) JP2003518768A (enExample)
KR (1) KR100794538B1 (enExample)
CN (1) CN1210773C (enExample)
AT (1) ATE431964T1 (enExample)
AU (1) AU2737301A (enExample)
DE (1) DE60042246D1 (enExample)
TW (1) TW471060B (enExample)
WO (1) WO2001048808A1 (enExample)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
WO2024128593A1 (ko) * 2022-12-12 2024-06-20 피에스케이 주식회사 기판 처리 장치 및 기판 처리 방법

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DE60119350T2 (de) * 2001-12-17 2007-03-15 Ami Semiconductor Belgium Bvba Methode zur Herstellung von Leiterbahnstrukturen
US6943039B2 (en) * 2003-02-11 2005-09-13 Applied Materials Inc. Method of etching ferroelectric layers
CN100444025C (zh) * 2004-07-12 2008-12-17 北京北方微电子基地设备工艺研究中心有限责任公司 光刻胶修整方法
US7597816B2 (en) * 2004-09-03 2009-10-06 Lam Research Corporation Wafer bevel polymer removal
US7413993B2 (en) * 2004-11-22 2008-08-19 Infineon Technologies Ag Process for removing a residue from a metal structure on a semiconductor substrate
JP4518986B2 (ja) * 2005-03-17 2010-08-04 東京エレクトロン株式会社 大気搬送室、被処理体の処理後搬送方法、プログラム及び記憶媒体
US20060246720A1 (en) * 2005-04-28 2006-11-02 Chii-Ming Wu Method to improve thermal stability of silicides with additives
US20070032081A1 (en) * 2005-08-08 2007-02-08 Jeremy Chang Edge ring assembly with dielectric spacer ring
US7479457B2 (en) * 2005-09-08 2009-01-20 Lam Research Corporation Gas mixture for removing photoresist and post etch residue from low-k dielectric material and method of use thereof
US20070227555A1 (en) * 2006-04-04 2007-10-04 Johnson Michael R Method to manipulate post metal etch/side wall residue
JP2014212310A (ja) * 2013-04-02 2014-11-13 東京エレクトロン株式会社 半導体デバイスの製造方法及び製造装置
JP6844083B2 (ja) * 2015-05-27 2021-03-17 サムコ株式会社 アフターコロージョン抑制処理方法
CN107464750B (zh) * 2017-08-23 2019-12-13 成都海威华芯科技有限公司 一种去除光刻胶底膜的工艺方法
US11749532B2 (en) 2021-05-04 2023-09-05 Applied Materials, Inc. Methods and apparatus for processing a substrate
US20250118532A1 (en) * 2023-10-09 2025-04-10 Tokyo Electron Limited System and method for plasma processing

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US5770100A (en) * 1989-08-28 1998-06-23 Fukuyama; Ryooji Method of treating samples

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JPH0341728A (ja) * 1989-07-07 1991-02-22 Fujitsu Ltd 半導体装置の製造方法
US5198634A (en) 1990-05-21 1993-03-30 Mattson Brad S Plasma contamination removal process
JP2998173B2 (ja) * 1990-06-01 2000-01-11 松下電器産業株式会社 Ａｌエッチング方法
WO1992000601A1 (fr) 1990-06-27 1992-01-09 Fujitsu Limited Procede de fabrication d'un circuit integre a semi-conducteurs et appareil de fabrication correspondant
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JPH05275325A (ja) * 1992-03-26 1993-10-22 Fujitsu Ltd 半導体装置の製造方法
US5462892A (en) 1992-06-22 1995-10-31 Vlsi Technology, Inc. Semiconductor processing method for preventing corrosion of metal film connections
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JPH08213366A (ja) * 1995-02-07 1996-08-20 Hitachi Ltd パターン形成方法およびパターン形成装置、ならびに半導体集積回路装置の製造方法および半導体製造装置
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Publication number Priority date Publication date Assignee Title
WO2024128593A1 (ko) * 2022-12-12 2024-06-20 피에스케이 주식회사 기판 처리 장치 및 기판 처리 방법

Also Published As

Publication number Publication date
JP2012023385A (ja) 2012-02-02
AU2737301A (en) 2001-07-09
DE60042246D1 (de) 2009-07-02
CN1434978A (zh) 2003-08-06
JP2003518768A (ja) 2003-06-10
TW471060B (en) 2002-01-01
EP1243023A1 (en) 2002-09-25
EP1243023B1 (en) 2009-05-20
US6852636B1 (en) 2005-02-08
ATE431964T1 (de) 2009-06-15
WO2001048808A1 (en) 2001-07-05
KR20020081234A (ko) 2002-10-26
CN1210773C (zh) 2005-07-13

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