ATE431964T1 - In-situ nachätzungs prozess zur entfernung von photoresist und seitenwandspassivierungsrückständen - Google Patents

In-situ nachätzungs prozess zur entfernung von photoresist und seitenwandspassivierungsrückständen

Info

Publication number
ATE431964T1
ATE431964T1 AT00990333T AT00990333T ATE431964T1 AT E431964 T1 ATE431964 T1 AT E431964T1 AT 00990333 T AT00990333 T AT 00990333T AT 00990333 T AT00990333 T AT 00990333T AT E431964 T1 ATE431964 T1 AT E431964T1
Authority
AT
Austria
Prior art keywords
etch
sidewall passivation
residue
etch process
remove photoresist
Prior art date
Application number
AT00990333T
Other languages
English (en)
Inventor
Robert O'donnell
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Application granted granted Critical
Publication of ATE431964T1 publication Critical patent/ATE431964T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02054Cleaning before device manufacture, i.e. Begin-Of-Line process combining dry and wet cleaning steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Removal Of Specific Substances (AREA)
AT00990333T 1999-12-27 2000-12-21 In-situ nachätzungs prozess zur entfernung von photoresist und seitenwandspassivierungsrückständen ATE431964T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/472,757 US6852636B1 (en) 1999-12-27 1999-12-27 Insitu post etch process to remove remaining photoresist and residual sidewall passivation
PCT/US2000/035165 WO2001048808A1 (en) 1999-12-27 2000-12-21 An insitu post etch process to remove remaining photoresist and residual sidewall passivation

Publications (1)

Publication Number Publication Date
ATE431964T1 true ATE431964T1 (de) 2009-06-15

Family

ID=23876824

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00990333T ATE431964T1 (de) 1999-12-27 2000-12-21 In-situ nachätzungs prozess zur entfernung von photoresist und seitenwandspassivierungsrückständen

Country Status (10)

Country Link
US (1) US6852636B1 (de)
EP (1) EP1243023B1 (de)
JP (2) JP2003518768A (de)
KR (1) KR100794538B1 (de)
CN (1) CN1210773C (de)
AT (1) ATE431964T1 (de)
AU (1) AU2737301A (de)
DE (1) DE60042246D1 (de)
TW (1) TW471060B (de)
WO (1) WO2001048808A1 (de)

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US6943039B2 (en) * 2003-02-11 2005-09-13 Applied Materials Inc. Method of etching ferroelectric layers
CN100444025C (zh) * 2004-07-12 2008-12-17 北京北方微电子基地设备工艺研究中心有限责任公司 光刻胶修整方法
US7597816B2 (en) * 2004-09-03 2009-10-06 Lam Research Corporation Wafer bevel polymer removal
US7413993B2 (en) * 2004-11-22 2008-08-19 Infineon Technologies Ag Process for removing a residue from a metal structure on a semiconductor substrate
JP4518986B2 (ja) * 2005-03-17 2010-08-04 東京エレクトロン株式会社 大気搬送室、被処理体の処理後搬送方法、プログラム及び記憶媒体
US20060246720A1 (en) * 2005-04-28 2006-11-02 Chii-Ming Wu Method to improve thermal stability of silicides with additives
US20070032081A1 (en) * 2005-08-08 2007-02-08 Jeremy Chang Edge ring assembly with dielectric spacer ring
US7479457B2 (en) * 2005-09-08 2009-01-20 Lam Research Corporation Gas mixture for removing photoresist and post etch residue from low-k dielectric material and method of use thereof
US20070227555A1 (en) * 2006-04-04 2007-10-04 Johnson Michael R Method to manipulate post metal etch/side wall residue
JP2014212310A (ja) * 2013-04-02 2014-11-13 東京エレクトロン株式会社 半導体デバイスの製造方法及び製造装置
JP6844083B2 (ja) * 2015-05-27 2021-03-17 サムコ株式会社 アフターコロージョン抑制処理方法
CN107464750B (zh) * 2017-08-23 2019-12-13 成都海威华芯科技有限公司 一种去除光刻胶底膜的工艺方法
US11749532B2 (en) 2021-05-04 2023-09-05 Applied Materials, Inc. Methods and apparatus for processing a substrate
KR20240086974A (ko) * 2022-12-12 2024-06-19 피에스케이 주식회사 기판 처리 장치 및 기판 처리 방법
US20250118532A1 (en) * 2023-10-09 2025-04-10 Tokyo Electron Limited System and method for plasma processing

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US4985113A (en) 1989-03-10 1991-01-15 Hitachi, Ltd. Sample treating method and apparatus
US5186718A (en) * 1989-05-19 1993-02-16 Applied Materials, Inc. Staged-vacuum wafer processing system and method
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Also Published As

Publication number Publication date
KR20020081234A (ko) 2002-10-26
TW471060B (en) 2002-01-01
EP1243023B1 (de) 2009-05-20
AU2737301A (en) 2001-07-09
US6852636B1 (en) 2005-02-08
KR100794538B1 (ko) 2008-01-17
CN1210773C (zh) 2005-07-13
JP2003518768A (ja) 2003-06-10
CN1434978A (zh) 2003-08-06
WO2001048808A1 (en) 2001-07-05
EP1243023A1 (de) 2002-09-25
DE60042246D1 (de) 2009-07-02
JP2012023385A (ja) 2012-02-02

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