DE60034999D1 - Auf geringe Leckage ausgerichtete Architektur für sub 0,18 Mikrometer salizidiertes CMOS Bauelement - Google Patents

Auf geringe Leckage ausgerichtete Architektur für sub 0,18 Mikrometer salizidiertes CMOS Bauelement

Info

Publication number
DE60034999D1
DE60034999D1 DE60034999T DE60034999T DE60034999D1 DE 60034999 D1 DE60034999 D1 DE 60034999D1 DE 60034999 T DE60034999 T DE 60034999T DE 60034999 T DE60034999 T DE 60034999T DE 60034999 D1 DE60034999 D1 DE 60034999D1
Authority
DE
Germany
Prior art keywords
nitride
trench
pad oxide
semiconductor substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60034999T
Other languages
English (en)
Other versions
DE60034999T2 (de
Inventor
Eng Hua Lim
Chong Wee Lim
Soh Yun Siah
Kong Hean Lee
Pei Ching Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Singapore Pte Ltd
Original Assignee
Chartered Semiconductor Manufacturing Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Manufacturing Pte Ltd filed Critical Chartered Semiconductor Manufacturing Pte Ltd
Application granted granted Critical
Publication of DE60034999D1 publication Critical patent/DE60034999D1/de
Publication of DE60034999T2 publication Critical patent/DE60034999T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60034999T 1999-07-16 2000-07-13 Auf geringe Leckage ausgerichtete Architektur für sub 0,18 Mikrometer salizidiertes CMOS Bauelement Expired - Fee Related DE60034999T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US356003 1999-07-16
US09/356,003 US6165871A (en) 1999-07-16 1999-07-16 Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device

Publications (2)

Publication Number Publication Date
DE60034999D1 true DE60034999D1 (de) 2007-07-12
DE60034999T2 DE60034999T2 (de) 2008-01-31

Family

ID=23399678

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60034999T Expired - Fee Related DE60034999T2 (de) 1999-07-16 2000-07-13 Auf geringe Leckage ausgerichtete Architektur für sub 0,18 Mikrometer salizidiertes CMOS Bauelement

Country Status (5)

Country Link
US (1) US6165871A (de)
EP (1) EP1069613B1 (de)
AT (1) ATE363731T1 (de)
DE (1) DE60034999T2 (de)
SG (1) SG81356A1 (de)

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KR100338766B1 (ko) * 1999-05-20 2002-05-30 윤종용 티(t)형 소자분리막 형성방법을 이용한 엘리베이티드 샐리사이드 소오스/드레인 영역 형성방법 및 이를 이용한 반도체 소자
US6277697B1 (en) * 1999-11-12 2001-08-21 United Microelectronics Corp. Method to reduce inverse-narrow-width effect
KR20010059185A (ko) * 1999-12-30 2001-07-06 박종섭 반도체소자의 소자분리막 형성방법
US6323104B1 (en) * 2000-03-01 2001-11-27 Micron Technology, Inc. Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry
US6265285B1 (en) * 2000-10-25 2001-07-24 Vanguard International Semiconductor Corporation Method of forming a self-aligned trench isolation
JP2003060024A (ja) * 2001-08-13 2003-02-28 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
US6541351B1 (en) * 2001-11-20 2003-04-01 International Business Machines Corporation Method for limiting divot formation in post shallow trench isolation processes
KR100458767B1 (ko) * 2002-07-04 2004-12-03 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
US6727150B2 (en) 2002-07-26 2004-04-27 Micron Technology, Inc. Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers
US6586314B1 (en) * 2002-10-08 2003-07-01 Chartered Semiconductor Manufacturing Ltd. Method of forming shallow trench isolation regions with improved corner rounding
KR100888150B1 (ko) * 2002-12-24 2009-03-16 동부일렉트로닉스 주식회사 반도체 소자의 트렌치 형성 방법
KR100958619B1 (ko) * 2002-12-31 2010-05-20 동부일렉트로닉스 주식회사 엔드 타입 플래시 메모리셀 제조방법
KR101012438B1 (ko) 2003-08-25 2011-02-08 매그나칩 반도체 유한회사 반도체 소자의 제조방법
US7238564B2 (en) * 2005-03-10 2007-07-03 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation structure
JP2006278754A (ja) * 2005-03-29 2006-10-12 Fujitsu Ltd 半導体装置及びその製造方法
KR100707593B1 (ko) * 2005-12-27 2007-04-13 동부일렉트로닉스 주식회사 반도체 소자의 이중 소자분리 구조 및 그 형성 방법
US20070149996A1 (en) * 2005-12-28 2007-06-28 Medtronic Vascular, Inc. Low profile filter
KR100932314B1 (ko) * 2007-08-24 2009-12-16 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US8765491B2 (en) 2010-10-28 2014-07-01 International Business Machines Corporation Shallow trench isolation recess repair using spacer formation process
US9111994B2 (en) * 2010-11-01 2015-08-18 Magnachip Semiconductor, Ltd. Semiconductor device and method of fabricating the same
US8623713B2 (en) * 2011-09-15 2014-01-07 International Business Machines Corporation Trench isolation structure
US8735991B2 (en) * 2011-12-01 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. High gate density devices and methods
CN103165507A (zh) * 2011-12-09 2013-06-19 上海华虹Nec电子有限公司 防止浅沟槽隔离边缘漏电的方法
US20140147985A1 (en) * 2012-11-29 2014-05-29 Freescale Semiconductor, Inc. Methods for the fabrication of semiconductor devices including sub-isolation buried layers
US9653507B2 (en) 2014-06-25 2017-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench isolation shrinkage method for enhanced device performance
KR101867755B1 (ko) * 2017-01-26 2018-06-15 매그나칩 반도체 유한회사 반도체 소자 및 그 제조 방법

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3324832B2 (ja) * 1993-07-28 2002-09-17 三菱電機株式会社 半導体装置およびその製造方法
KR0151051B1 (ko) * 1995-05-30 1998-12-01 김광호 반도체장치의 절연막 형성방법
KR100197648B1 (ko) * 1995-08-26 1999-06-15 김영환 반도체소자의 소자분리 절연막 형성방법
KR0168194B1 (ko) * 1995-12-14 1999-02-01 김광호 반도체 소자의 소자분리막 형성방법
KR100192178B1 (ko) * 1996-01-11 1999-06-15 김영환 반도체 소자의 아이솔레이션 방법
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
KR100195243B1 (ko) * 1996-09-05 1999-06-15 윤종용 얕은 트랜치 분리를 이용한 반도체 장치의 제조방법
US5895253A (en) * 1997-08-22 1999-04-20 Micron Technology, Inc. Trench isolation for CMOS devices
US5801083A (en) * 1997-10-20 1998-09-01 Chartered Semiconductor Manufacturing, Ltd. Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners
US6020030A (en) * 1998-05-07 2000-02-01 Aluminum Company Of America Coating an aluminum alloy substrate

Also Published As

Publication number Publication date
DE60034999T2 (de) 2008-01-31
SG81356A1 (en) 2001-06-19
ATE363731T1 (de) 2007-06-15
EP1069613A3 (de) 2004-08-18
EP1069613B1 (de) 2007-05-30
EP1069613A2 (de) 2001-01-17
US6165871A (en) 2000-12-26

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