DE60031737D1 - Frequenzregelkreis - Google Patents

Frequenzregelkreis

Info

Publication number
DE60031737D1
DE60031737D1 DE60031737T DE60031737T DE60031737D1 DE 60031737 D1 DE60031737 D1 DE 60031737D1 DE 60031737 T DE60031737 T DE 60031737T DE 60031737 T DE60031737 T DE 60031737T DE 60031737 D1 DE60031737 D1 DE 60031737D1
Authority
DE
Germany
Prior art keywords
control circuit
frequency control
frequency
circuit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60031737T
Other languages
English (en)
Other versions
DE60031737T2 (de
Inventor
Jacques M Majos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zarbana Digital Fund LLC
Original Assignee
Fahrenheit Thermoscope LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fahrenheit Thermoscope LLC filed Critical Fahrenheit Thermoscope LLC
Publication of DE60031737D1 publication Critical patent/DE60031737D1/de
Application granted granted Critical
Publication of DE60031737T2 publication Critical patent/DE60031737T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE60031737T 1999-04-30 2000-04-19 Frequenzregelkreis Expired - Lifetime DE60031737T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9905627 1999-04-30
FR9905627A FR2793091B1 (fr) 1999-04-30 1999-04-30 Dispositif d'asservissement de frequence

Publications (2)

Publication Number Publication Date
DE60031737D1 true DE60031737D1 (de) 2006-12-21
DE60031737T2 DE60031737T2 (de) 2007-09-20

Family

ID=9545176

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60031737T Expired - Lifetime DE60031737T2 (de) 1999-04-30 2000-04-19 Frequenzregelkreis

Country Status (5)

Country Link
US (2) US6701445B1 (de)
EP (1) EP1049285B1 (de)
JP (1) JP4628517B2 (de)
DE (1) DE60031737T2 (de)
FR (1) FR2793091B1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10132403A1 (de) * 2001-07-09 2003-01-23 Alcatel Sa Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal
US6777993B1 (en) * 2001-08-07 2004-08-17 Altera Corporation Method and apparatus for adjusting the phase and frequency of a periodic wave
JP3559781B2 (ja) * 2001-12-27 2004-09-02 エヌティティエレクトロニクス株式会社 位相同期回路
DE60306424T2 (de) * 2002-12-13 2007-02-01 Koninklijke Philips Electronics N.V. Verriegelte regelkreise mit niedriger verriegelungszeitverzögerung mit der verwendung einer zeitzyklusunterdrückungsvorrichtung
KR100546327B1 (ko) * 2003-06-03 2006-01-26 삼성전자주식회사 피드백 제어 시스템 및 방법
US7475270B1 (en) * 2003-11-03 2009-01-06 Hewlett-Packard Development Company, L.P. System and method for waveform sampling
US7046057B1 (en) * 2003-11-03 2006-05-16 Hewlett-Packard Development Company, L.P. System and method for synchronizing devices
US7855584B2 (en) * 2003-12-09 2010-12-21 St-Ericsson Sa Low lock time delay locked loops using time cycle suppressor
JP2005328109A (ja) * 2004-05-12 2005-11-24 Thine Electronics Inc 等位相多相クロック信号発生回路およびそれを用いたシリアルディジタルデータ受信回路
CN100338875C (zh) * 2004-11-12 2007-09-19 鸿富锦精密工业（深圳）有限公司 时钟信号发生器
US7084790B2 (en) * 2004-12-07 2006-08-01 Stmicroelectronics S.R.L. Device to effectuate a digital estimate of a periodic electric signal, related method and control system for an electric motor which comprises said device
US7157953B1 (en) * 2005-04-12 2007-01-02 Xilinx, Inc. Circuit for and method of employing a clock signal
CN1960183B (zh) * 2005-10-31 2010-07-28 盛群半导体股份有限公司 自动调整的高准确性振荡器
JP4404087B2 (ja) * 2006-11-29 2010-01-27 コニカミノルタビジネステクノロジーズ株式会社 周波数可変クロック出力回路及び同装置、モータ駆動装置びに画像形成装置
JP2009159038A (ja) * 2007-12-25 2009-07-16 Hitachi Ltd Ｐｌｌ回路
JP2010056888A (ja) * 2008-08-28 2010-03-11 Elpida Memory Inc 同期化制御回路、半導体装置及び制御方法
JP2011060364A (ja) * 2009-09-08 2011-03-24 Elpida Memory Inc クロック生成回路及びこれを備える半導体装置並びにデータ処理システム
US8933733B2 (en) * 2013-01-07 2015-01-13 Mediatek Singapore Pte. Ltd. Method and system for fast synchronized dynamic switching of a reconfigurable phase locked loop (PLL) for near field communications (NFC) peer to peer (P2P) active communications
US9287884B2 (en) * 2013-02-21 2016-03-15 Microchip Technology Incorporated Enhanced numerical controlled oscillator
US9438204B2 (en) * 2013-08-27 2016-09-06 Mediatek Inc. Signal processing device and signal processing method
JP2022098601A (ja) * 2020-12-22 2022-07-04 ルネサスエレクトロニクス株式会社 位相同期回路

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5266346A (en) * 1975-11-29 1977-06-01 Tokyo Electric Co Ltd Synch. clock control of microcomputer system
US4031478A (en) * 1976-06-29 1977-06-21 International Telephone And Telegraph Corporation Digital phase/frequency comparator
US4030045A (en) * 1976-07-06 1977-06-14 International Telephone And Telegraph Corporation Digital double differential phase-locked loop
JPS58111527A (ja) * 1981-12-25 1983-07-02 Fujitsu Ltd 周波数比較回路
US4456890A (en) * 1982-04-05 1984-06-26 Computer Peripherals Inc. Data tracking clock recovery system using digitally controlled oscillator
JPS6047515A (ja) 1983-08-26 1985-03-14 Victor Co Of Japan Ltd 同期引込判別回路
JPS6070827A (ja) * 1983-09-27 1985-04-22 Fujitsu Ltd 位相調整方式
US4682343A (en) * 1984-09-11 1987-07-21 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Processing circuit with asymmetry corrector and convolutional encoder for digital data
JPS61216524A (ja) 1985-03-22 1986-09-26 Hitachi Ltd 位相同期検出回路
DE3722328A1 (de) * 1987-07-07 1989-01-19 Broadcast Television Syst Schaltungsanordnung zur gewinnung eines taktsignals
FR2618958B1 (fr) 1987-07-29 1995-04-21 Radiotechnique Compelec Synthetiseur de frequences presentant un dispositif indicateur d'accord
US4912730A (en) * 1988-10-03 1990-03-27 Harris Corporation High speed reception of encoded data utilizing dual phase resynchronizing clock recovery
JP2828286B2 (ja) 1989-11-16 1998-11-25 富士通株式会社 Ｐｌｌのロック検出回路
JP3232351B2 (ja) * 1993-10-06 2001-11-26 三菱電機株式会社 デジタル回路装置
US5530383A (en) * 1994-12-05 1996-06-25 May; Michael R. Method and apparatus for a frequency detection circuit for use in a phase locked loop
JP2919378B2 (ja) * 1996-08-29 1999-07-12 日本電気アイシーマイコンシステム株式会社 Ｐｌｌ回路
JP3179382B2 (ja) * 1997-08-27 2001-06-25 山形日本電気株式会社 Ｐｌｌ回路
US6266799B1 (en) * 1997-10-02 2001-07-24 Xaqti, Corporation Multi-phase data/clock recovery circuitry and methods for implementing same
US6060953A (en) * 1998-04-08 2000-05-09 Winbond Electronics Corporation PLL response time accelerating system using a frequency detector counter

Also Published As

Publication number Publication date
EP1049285A1 (de) 2000-11-02
FR2793091B1 (fr) 2001-06-08
FR2793091A1 (fr) 2000-11-03
USRE41031E1 (en) 2009-12-01
JP4628517B2 (ja) 2011-02-09
EP1049285B1 (de) 2006-11-08
DE60031737T2 (de) 2007-09-20
JP2000341113A (ja) 2000-12-08
US6701445B1 (en) 2004-03-02

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