DE60002589T2 - System und verfahren zur initialisierung von serieller datenübertragung zwischen zwei taktbereichen - Google Patents

System und verfahren zur initialisierung von serieller datenübertragung zwischen zwei taktbereichen Download PDF

Info

Publication number
DE60002589T2
DE60002589T2 DE60002589T DE60002589T DE60002589T2 DE 60002589 T2 DE60002589 T2 DE 60002589T2 DE 60002589 T DE60002589 T DE 60002589T DE 60002589 T DE60002589 T DE 60002589T DE 60002589 T2 DE60002589 T2 DE 60002589T2
Authority
DE
Germany
Prior art keywords
clock
bits
ratio
clock rate
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60002589T
Other languages
German (de)
English (en)
Other versions
DE60002589D1 (de
Inventor
R. Derrick MEYER
S. Philip MADRID
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE60002589D1 publication Critical patent/DE60002589D1/de
Publication of DE60002589T2 publication Critical patent/DE60002589T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Power Sources (AREA)
DE60002589T 1999-08-31 2000-03-23 System und verfahren zur initialisierung von serieller datenübertragung zwischen zwei taktbereichen Expired - Lifetime DE60002589T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US386650 1989-07-31
US09/386,650 US6393502B1 (en) 1999-08-31 1999-08-31 System and method for initiating a serial data transfer between two clock domains
PCT/US2000/007695 WO2001016773A1 (en) 1999-08-31 2000-03-23 System and method for initiating a serial data transfer between two clock domains

Publications (2)

Publication Number Publication Date
DE60002589D1 DE60002589D1 (de) 2003-06-12
DE60002589T2 true DE60002589T2 (de) 2004-03-25

Family

ID=23526484

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60002589T Expired - Lifetime DE60002589T2 (de) 1999-08-31 2000-03-23 System und verfahren zur initialisierung von serieller datenübertragung zwischen zwei taktbereichen

Country Status (6)

Country Link
US (3) US6393502B1 (https=)
EP (1) EP1214662B1 (https=)
JP (1) JP4630512B2 (https=)
KR (1) KR100734528B1 (https=)
DE (1) DE60002589T2 (https=)
WO (1) WO2001016773A1 (https=)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4091195B2 (ja) * 1999-02-08 2008-05-28 富士通株式会社 インタフェース制御装置及びインタフェース制御方法
US6535565B1 (en) * 1999-03-16 2003-03-18 Level One Communications, Inc. Receiver rate converter phase calculation apparatus and method
US6584575B1 (en) * 1999-08-31 2003-06-24 Advanced Micro Devices, Inc. System and method for initializing source-synchronous data transfers using ratio bits
US7039074B1 (en) * 2000-09-14 2006-05-02 Agiletv Corporation N-way demultiplexer
US7047196B2 (en) 2000-06-08 2006-05-16 Agiletv Corporation System and method of voice recognition near a wireline node of a network supporting cable television and/or video delivery
KR100369768B1 (ko) 2000-12-09 2003-03-03 엘지전자 주식회사 휴대용 컴퓨터에서의 버스 클럭 주파수 제어장치
US6715094B2 (en) * 2000-12-20 2004-03-30 Intel Corporation Mult-mode I/O interface for synchronizing selected control patterns into control clock domain to obtain interface control signals to be transmitted to I/O buffers
US8095370B2 (en) 2001-02-16 2012-01-10 Agiletv Corporation Dual compression voice recordation non-repudiation system
US6952174B2 (en) * 2001-09-07 2005-10-04 Microsemi Corporation Serial data interface
US6959398B2 (en) * 2001-12-31 2005-10-25 Hewlett-Packard Development Company, L.P. Universal asynchronous boundary module
US8219736B2 (en) * 2002-02-12 2012-07-10 Ati Technologies Ulc Method and apparatus for a data bridge in a computer system
US6898725B2 (en) * 2002-03-27 2005-05-24 International Business Machines Corporation Method for adjusting system clocks using dynamic clock ratio detector to detect clock ratio between clock domain of driver and counting receiver clock domain
JP4159415B2 (ja) 2002-08-23 2008-10-01 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP2004112182A (ja) * 2002-09-17 2004-04-08 Fuji Xerox Co Ltd 通信端末装置及びその制御方法
US7324589B2 (en) * 2003-02-05 2008-01-29 Fujitsu Limited Method and system for providing error compensation to a signal using feedback control
US7313210B2 (en) * 2003-02-28 2007-12-25 Hewlett-Packard Development Company, L.P. System and method for establishing a known timing relationship between two clock signals
US20040193931A1 (en) * 2003-03-26 2004-09-30 Akkerman Ryan L. System and method for transferring data from a first clock domain to a second clock domain
US7275171B2 (en) * 2003-05-22 2007-09-25 Rambus Inc. Method and apparatus for programmable sampling clock edge selection
EP1515271A1 (en) * 2003-09-09 2005-03-16 STMicroelectronics S.r.l. Method and device for extracting a subset of data from a set of data
US7657689B1 (en) * 2003-10-07 2010-02-02 Altera Corporation Methods and apparatus for handling reset events in a bus bridge
FR2870368B1 (fr) * 2004-01-27 2006-12-15 Atmel Corp Procede et dispositif pour piloter de multiples peripheriques avec des frequences d'horloge differentes dans un circuit integre
US20060023819A1 (en) * 2004-07-29 2006-02-02 Adkisson Richard W Clock synchronizer
US7436917B2 (en) * 2004-07-29 2008-10-14 Hewlett-Packard Development Company, L.P. Controller for clock synchronizer
US8660647B2 (en) * 2005-07-28 2014-02-25 Cyberonics, Inc. Stimulating cranial nerve to treat pulmonary disorder
US7614737B2 (en) * 2005-12-16 2009-11-10 Lexmark International Inc. Method for identifying an installed cartridge
KR20070114557A (ko) * 2006-05-29 2007-12-04 삼성전자주식회사 퓨즈를 갖는 반도체 기억 소자 및 그 형성 방법
US7760798B2 (en) * 2006-05-30 2010-07-20 Fujitsu Limited System and method for adjusting compensation applied to a signal
US7839958B2 (en) 2006-05-30 2010-11-23 Fujitsu Limited System and method for the adjustment of compensation applied to a signal
US7817757B2 (en) * 2006-05-30 2010-10-19 Fujitsu Limited System and method for independently adjusting multiple offset compensations applied to a signal
US7804921B2 (en) 2006-05-30 2010-09-28 Fujitsu Limited System and method for decoupling multiple control loops
US7848470B2 (en) * 2006-05-30 2010-12-07 Fujitsu Limited System and method for asymmetrically adjusting compensation applied to a signal
US7839955B2 (en) * 2006-05-30 2010-11-23 Fujitsu Limited System and method for the non-linear adjustment of compensation applied to a signal
US7764757B2 (en) * 2006-05-30 2010-07-27 Fujitsu Limited System and method for the adjustment of offset compensation applied to a signal
US7817712B2 (en) * 2006-05-30 2010-10-19 Fujitsu Limited System and method for independently adjusting multiple compensations applied to a signal
US7804894B2 (en) 2006-05-30 2010-09-28 Fujitsu Limited System and method for the adjustment of compensation applied to a signal using filter patterns
US7787534B2 (en) * 2006-05-30 2010-08-31 Fujitsu Limited System and method for adjusting offset compensation applied to a signal
US7801208B2 (en) * 2006-05-30 2010-09-21 Fujitsu Limited System and method for adjusting compensation applied to a signal using filter patterns
CN101617371B (zh) * 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
US7466247B1 (en) 2007-10-04 2008-12-16 Lecroy Corporation Fractional-decimation signal processing
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8467486B2 (en) * 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US9197981B2 (en) * 2011-04-08 2015-11-24 The Regents Of The University Of Michigan Coordination amongst heterogeneous wireless devices
US9858322B2 (en) 2013-11-11 2018-01-02 Amazon Technologies, Inc. Data stream ingestion and persistence techniques
FR3029661B1 (fr) * 2014-12-04 2016-12-09 Stmicroelectronics Rousset Procedes de transmission et de reception d'un signal binaire sur un lien serie, en particulier pour la detection de la vitesse de transmission, et dispositifs correspondants
US9825730B1 (en) * 2016-09-26 2017-11-21 Dell Products, Lp System and method for optimizing link performance with lanes operating at different speeds
DE102019112447A1 (de) * 2019-05-13 2020-11-19 Jenoptik Optical Systems Gmbh Verfahren und Auswerteeinheit zur Ermittlung eines Zeitpunkts einer Flanke in einem Signal
US11860685B2 (en) 2021-10-29 2024-01-02 Advanced Micro Devices, Inc. Clock frequency divider circuit

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725793A (en) 1971-12-15 1973-04-03 Bell Telephone Labor Inc Clock synchronization arrangement employing delay devices
JPS5911056A (ja) * 1982-07-09 1984-01-20 Nec Corp 調歩同期式通信方式
JPS61169956A (ja) * 1985-01-23 1986-07-31 Fujitsu Ltd デ−タ転送速度同期方式
DE3643766A1 (de) 1986-12-20 1988-07-07 Standard Elektrik Lorenz Ag Datenbussystem fuer einen seriellen datenbus
KR900001817B1 (ko) 1987-08-01 1990-03-24 삼성전자 주식회사 저항 수단을 이용한 씨 모스 티티엘 인푸트 버퍼
JPH07114348B2 (ja) 1987-12-11 1995-12-06 日本電気株式会社 論理回路
JPH01194548A (ja) * 1988-01-28 1989-08-04 Fujitsu Ltd 調歩同期式データ伝送の速度設定方式
JPH07120225B2 (ja) 1988-04-15 1995-12-20 富士通株式会社 半導体回路装置
US4989175A (en) 1988-11-25 1991-01-29 Unisys Corp. High speed on-chip clock phase generating system
JP2559237Y2 (ja) * 1989-01-23 1998-01-14 旭光学工業株式会社 シリアルデータサンプリング信号発生装置
JPH02202738A (ja) * 1989-02-01 1990-08-10 Fujitsu Ltd シリアルデータ受信回路
US5058132A (en) 1989-10-26 1991-10-15 National Semiconductor Corporation Clock distribution system and technique
JPH0377543U (https=) * 1989-11-28 1991-08-05
US5295257A (en) * 1991-05-24 1994-03-15 Alliedsignal Inc. Distributed multiple clock system and a method for the synchronization of a distributed multiple system
US5307381A (en) 1991-12-27 1994-04-26 Intel Corporation Skew-free clock signal distribution network in a microprocessor
GB2265283B (en) * 1992-03-18 1995-10-25 Crystal Semiconductor Corp Resynchronization of a synchronous serial interface
US5459855A (en) * 1992-08-10 1995-10-17 Hewlett-Packard Company Frequency ratio detector for determining fixed frequency ratios in a computer system
US5256994A (en) 1992-09-21 1993-10-26 Intel Corporation Programmable secondary clock generator
CA2124709C (en) * 1993-08-24 1998-06-09 Lee-Fang Wei Reduced speed equalizer
JP3402498B2 (ja) * 1993-12-24 2003-05-06 パイオニア株式会社 車載用電子機器
US6112307A (en) * 1993-12-30 2000-08-29 Intel Corporation Method and apparatus for translating signals between clock domains of different frequencies
JP3466738B2 (ja) 1994-11-21 2003-11-17 ヤマハ株式会社 非同期シリアルデータ受信装置
US5550780A (en) * 1994-12-19 1996-08-27 Cirrus Logic, Inc. Two cycle asynchronous FIFO queue
SE515563C2 (sv) * 1995-01-11 2001-08-27 Ericsson Telefon Ab L M Dataöverföringssystem
US6169772B1 (en) * 1995-04-07 2001-01-02 Via-Cyrix, Inc. Stretching setup and hold times in synchronous designs
US5825834A (en) * 1995-10-13 1998-10-20 Vlsi Technlogy, Inc. Fast response system implementing a sampling clock for extracting stable clock information from a serial data stream with defined jitter characeristics and method therefor
US5859881A (en) * 1996-06-07 1999-01-12 International Business Machines Corporation Adaptive filtering method and apparatus to compensate for a frequency difference between two clock sources
GB2315197B (en) * 1996-07-11 2000-07-12 Nokia Mobile Phones Ltd Method and apparatus for system clock adjustment
JP3582238B2 (ja) * 1996-07-15 2004-10-27 松下電器産業株式会社 信号判定器およびこれを用いた無線装置
US5909563A (en) * 1996-09-25 1999-06-01 Philips Electronics North America Corporation Computer system including an interface for transferring data between two clock domains
US6055645A (en) * 1996-12-30 2000-04-25 Intel Corporation Method and apparatus for providing a clock signal to a processor
GB2321351B (en) * 1997-01-17 1999-03-10 Paul Flood System and method for data transfer across multiple clock domains
US6061410A (en) * 1997-02-27 2000-05-09 Advanced Micro Devices Frequency ratio estimation arrangement and method thereof
US6202108B1 (en) * 1997-03-13 2001-03-13 Bull S.A. Process and system for initializing a serial link between two integrated circuits comprising a parallel-serial port using two clocks with different frequencies
KR100230451B1 (ko) * 1997-04-08 1999-11-15 윤종용 디지털 신호처리 프로세서의 비동기방식 직렬데이터 송수신 방법
JPH10322404A (ja) * 1997-05-19 1998-12-04 Sharp Corp シリアルデータ通信方法および装置
FR2764758B1 (fr) * 1997-06-12 1999-08-06 Scm Schneider Microsysteme Mic Procede de mesure automatique de l'unite de temps pour peripheriques de communication dedies aux cartes a puce
US6249555B1 (en) * 1997-07-14 2001-06-19 Grass Valley (Us) Inc. Low jitter digital extraction of data from serial bitstreams
US6000022A (en) * 1997-10-10 1999-12-07 Micron Technology, Inc. Method and apparatus for coupling signals between two circuits operating in different clock domains
US6269136B1 (en) * 1998-02-02 2001-07-31 Microunity Systems Engineering, Inc. Digital differential analyzer data synchronizer
US6260152B1 (en) * 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
US6128678A (en) * 1998-08-28 2000-10-03 Theseus Logic, Inc. FIFO using asynchronous logic to interface between clocked logic circuits
US6000107A (en) * 1998-09-15 1999-12-14 West; Stephen W. Fastening device
US6321342B1 (en) * 1999-03-23 2001-11-20 Lsi Logic Corporation Method and apparatus for interfacing circuits that operate based upon different clock signals
US6172540B1 (en) * 1999-08-16 2001-01-09 Intel Corporation Apparatus for fast logic transfer of data across asynchronous clock domains
US6327207B1 (en) * 2001-04-09 2001-12-04 Lsi Logic Corporation Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding

Also Published As

Publication number Publication date
US6505261B1 (en) 2003-01-07
EP1214662B1 (en) 2003-05-07
KR100734528B1 (ko) 2007-07-03
KR20020064277A (ko) 2002-08-07
WO2001016773A1 (en) 2001-03-08
EP1214662A1 (en) 2002-06-19
JP4630512B2 (ja) 2011-02-09
DE60002589D1 (de) 2003-06-12
US6393502B1 (en) 2002-05-21
US6668292B2 (en) 2003-12-23
US20020090046A1 (en) 2002-07-11
JP2003508956A (ja) 2003-03-04

Similar Documents

Publication Publication Date Title
DE60002589T2 (de) System und verfahren zur initialisierung von serieller datenübertragung zwischen zwei taktbereichen
DE69120586T2 (de) Rechnersystem mit synchronem Bus
DE69634358T2 (de) Verzögerungsverringerung in der übertragung von gepufferten daten zwischenzwei gegenseitig asynchronen bussen
DE69124905T2 (de) Datenverarbeitungsvorrichtung zur dynamischen Zeiteinstellung in einem dynamischen Speichersystem
DE19580707C2 (de) PCI-ZU-ISA-Interrupt-Protokoll-Konverter und -Auswahlmechanismus
DE69934401T2 (de) Datenerfassungssystem mit mitteln zur analyse und zum abspeichern in echtzeit
DE69122585T2 (de) Rekonfigurierbares Mehrzwecksystem zum Verarbeiten serieller Bitströme
DE3218741A1 (de) Datentransfersystem
DE69710515T2 (de) Verfahren und Vorrichtung zur Bestimmung von Wartezuständen auf einer Zyklusbasis in einem Datenverarbeitungssystem
DE69433130T2 (de) Rechnersystem mit verändertem lokalen Datenbus
DE102015102760B4 (de) Taktlose serielle Slave-Vorrichtung
EP0689747B1 (de) Bitratenerkennung
DE4018481C2 (https=)
DE69814005T2 (de) Verfahren und Vorrichtung zum sicheren Datenrundsenden über einen PCI-bus
DE69225535T2 (de) Deterministisches Verfahren zur Zuordnung eines gemeinsamen Betriebsmittels
DE19709210A1 (de) RAM-Speicherschaltung
DE3751083T2 (de) Schnittstelle für seriellen Bus, fähig für den Datentransfer in verschiedenen Formaten.
DE69432063T2 (de) Bussteuereinrichtung
DE69119147T2 (de) Erweiterungskarte mit mehreren Geschwindigkeiten
DE69428953T2 (de) Prioritätskodierer
DE69024913T2 (de) Programmierbare Steuerungsvorrichtung mit Unterbrechungssteuerungsgerät zur Prioritätsbestimmung von Unterbrechungsanforderungen von einer Vielzahl von Ein-/Ausgabeeinrichtungen und zur Unterbrechungsvektorerzeugung
DE3789914T2 (de) Vorrichtung zur Bestimmung der Prioritätsordnung.
DE69128319T2 (de) Arbeitsplatz mit Stossbetriebdatenübertragung
DE2726679A1 (de) Kanalsteuerung fuer datenverarbeitungsanlagen und verfahren zu ihrem betrieb
DE10110567A1 (de) Datenverarbeitungssystem mit einstellbaren Takten für unterteilte synchrone Schnittstellen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY