DE3940674A1 - Halbleiteranordnung und verfahren zu ihrer herstellung - Google Patents

Halbleiteranordnung und verfahren zu ihrer herstellung

Info

Publication number
DE3940674A1
DE3940674A1 DE3940674A DE3940674A DE3940674A1 DE 3940674 A1 DE3940674 A1 DE 3940674A1 DE 3940674 A DE3940674 A DE 3940674A DE 3940674 A DE3940674 A DE 3940674A DE 3940674 A1 DE3940674 A1 DE 3940674A1
Authority
DE
Germany
Prior art keywords
layer
insulating layer
semiconductor layer
conductivity type
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3940674A
Other languages
German (de)
English (en)
Other versions
DE3940674C2 (enExample
Inventor
Toshio Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63322060A external-priority patent/JPH02168627A/ja
Priority claimed from JP63322061A external-priority patent/JPH02168628A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3940674A1 publication Critical patent/DE3940674A1/de
Application granted granted Critical
Publication of DE3940674C2 publication Critical patent/DE3940674C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/441—Vertical BJTs having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/018—Manufacture or treatment of isolation regions comprising dielectric materials using selective deposition of crystalline silicon, e.g. using epitaxial growth of silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials

Landscapes

  • Bipolar Transistors (AREA)
DE3940674A 1988-12-22 1989-12-08 Halbleiteranordnung und verfahren zu ihrer herstellung Granted DE3940674A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63322060A JPH02168627A (ja) 1988-12-22 1988-12-22 半導体装置及びその製造方法
JP63322061A JPH02168628A (ja) 1988-12-22 1988-12-22 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3940674A1 true DE3940674A1 (de) 1990-06-28
DE3940674C2 DE3940674C2 (enExample) 1992-01-16

Family

ID=26570673

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3940674A Granted DE3940674A1 (de) 1988-12-22 1989-12-08 Halbleiteranordnung und verfahren zu ihrer herstellung

Country Status (2)

Country Link
US (1) US5001533A (enExample)
DE (1) DE3940674A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0490111A1 (en) * 1990-12-07 1992-06-17 International Business Machines Corporation A low capacitance bipolar junction transistor and fabrication process therefor
FR2728387A1 (fr) * 1994-12-13 1996-06-21 Korea Electronics Telecomm Procede de fabrication d'un transistor bipolaire
DE19842106A1 (de) * 1998-09-08 2000-03-09 Inst Halbleiterphysik Gmbh Vertikaler Bipolartransistor und Verfahren zu seiner Herstellung
DE10134089A1 (de) * 2001-07-13 2003-01-30 Infineon Technologies Ag Verfahren zur Herstellung eines Bipolartransistors mit Polysiliziumemitter

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148252A (en) * 1990-02-13 1992-09-15 Kabushiki Kaisha Toshiba Bipolar transistor
US5355015A (en) * 1990-12-13 1994-10-11 National Semiconductor Corporation High breakdown lateral PNP transistor
JPH0529254A (ja) * 1991-07-24 1993-02-05 Sony Corp 配線形成方法
JP2861856B2 (ja) 1995-03-30 1999-02-24 日本電気株式会社 半導体装置の製造方法
JP2907323B2 (ja) * 1995-12-06 1999-06-21 日本電気株式会社 半導体装置およびその製造方法
KR100286349B1 (ko) 1999-04-19 2001-03-15 김영환 반도체 소자의 제조방법
EP1152462A1 (de) * 2000-05-05 2001-11-07 Infineon Technologies AG Verfahren zur Herstellung eines Bipolartransistors
JP2003045884A (ja) * 2001-07-31 2003-02-14 Fujitsu Ltd 半導体装置及びその製造方法
US6759730B2 (en) 2001-09-18 2004-07-06 Agere Systems Inc. Bipolar junction transistor compatible with vertical replacement gate transistor
DE10162074B4 (de) * 2001-12-06 2010-04-08 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik BiCMOS-Struktur, Verfahren zu ihrer Herstellung und Bipolartransistor für eine BiCMOS-Struktur
DE10249897B4 (de) * 2002-10-25 2005-09-22 Austriamicrosystems Ag Selbstjustierendes Verfahren zur Herstellung eines Transistors
WO2006109208A2 (en) * 2005-04-13 2006-10-19 Nxp B.V. Method of fabricating a heterojunction bipolar transistor
CN101167167A (zh) * 2005-04-28 2008-04-23 Nxp股份有限公司 双极晶体管及其制造方法
JP5112648B2 (ja) * 2006-05-29 2013-01-09 セイコーインスツル株式会社 半導体装置
DE102016216084B8 (de) * 2016-08-26 2021-12-23 Infineon Technologies Dresden Gmbh Verfahren zum Herstellen eines Bipolartransistors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208872A (ja) * 1985-03-14 1986-09-17 Sony Corp 半導体装置の製造方法
US4710241A (en) * 1985-01-17 1987-12-01 Kabushiki Kaisha Toshiba Method of making a bipolar semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS561556A (en) * 1979-06-18 1981-01-09 Hitachi Ltd Semiconductor device
JPS59217364A (ja) * 1983-05-26 1984-12-07 Sony Corp 半導体装置の製法
US4797372A (en) * 1985-11-01 1989-01-10 Texas Instruments Incorporated Method of making a merge bipolar and complementary metal oxide semiconductor transistor device
US4782030A (en) * 1986-07-09 1988-11-01 Kabushiki Kaisha Toshiba Method of manufacturing bipolar semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710241A (en) * 1985-01-17 1987-12-01 Kabushiki Kaisha Toshiba Method of making a bipolar semiconductor device
JPS61208872A (ja) * 1985-03-14 1986-09-17 Sony Corp 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0490111A1 (en) * 1990-12-07 1992-06-17 International Business Machines Corporation A low capacitance bipolar junction transistor and fabrication process therefor
FR2728387A1 (fr) * 1994-12-13 1996-06-21 Korea Electronics Telecomm Procede de fabrication d'un transistor bipolaire
DE19842106A1 (de) * 1998-09-08 2000-03-09 Inst Halbleiterphysik Gmbh Vertikaler Bipolartransistor und Verfahren zu seiner Herstellung
US6627972B1 (en) 1998-09-08 2003-09-30 Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh Vertical bipolar transistor
DE10134089A1 (de) * 2001-07-13 2003-01-30 Infineon Technologies Ag Verfahren zur Herstellung eines Bipolartransistors mit Polysiliziumemitter
US7060583B2 (en) 2001-07-13 2006-06-13 Infineon Technologies Ag Method for manufacturing a bipolar transistor having a polysilicon emitter

Also Published As

Publication number Publication date
DE3940674C2 (enExample) 1992-01-16
US5001533A (en) 1991-03-19

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee