DE3885637D1 - Verfahren zur Herstellung von gleichmässigen Materialschichten. - Google Patents
Verfahren zur Herstellung von gleichmässigen Materialschichten.Info
- Publication number
- DE3885637D1 DE3885637D1 DE88103610T DE3885637T DE3885637D1 DE 3885637 D1 DE3885637 D1 DE 3885637D1 DE 88103610 T DE88103610 T DE 88103610T DE 3885637 T DE3885637 T DE 3885637T DE 3885637 D1 DE3885637 D1 DE 3885637D1
- Authority
- DE
- Germany
- Prior art keywords
- production
- uniform layers
- uniform
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/959—Mechanical polishing of wafer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/031,809 US4735679A (en) | 1987-03-30 | 1987-03-30 | Method of improving silicon-on-insulator uniformity |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3885637D1 true DE3885637D1 (de) | 1993-12-23 |
DE3885637T2 DE3885637T2 (de) | 1994-05-11 |
Family
ID=21861510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE88103610T Expired - Fee Related DE3885637T2 (de) | 1987-03-30 | 1988-03-08 | Verfahren zur Herstellung von gleichmässigen Materialschichten. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4735679A (de) |
EP (1) | EP0284840B1 (de) |
JP (1) | JP2661089B2 (de) |
CA (1) | CA1247259A (de) |
DE (1) | DE3885637T2 (de) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8700033A (nl) * | 1987-01-09 | 1988-08-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting van het type halfgeleider op isolator. |
NL8800953A (nl) * | 1988-04-13 | 1989-11-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderlichaam. |
DE68927871T2 (de) * | 1988-11-09 | 1997-07-03 | Sony Corp | Herstellungsverfahren eines Halbleiterwafers |
US4874463A (en) * | 1988-12-23 | 1989-10-17 | At&T Bell Laboratories | Integrated circuits from wafers having improved flatness |
FR2651068B1 (fr) * | 1989-08-16 | 1994-06-10 | France Etat | Procede de fabrication de transistor mos mesa de type silicium sur isolant |
US5110755A (en) * | 1990-01-04 | 1992-05-05 | Westinghouse Electric Corp. | Process for forming a component insulator on a silicon substrate |
US5142828A (en) * | 1990-06-25 | 1992-09-01 | Microelectronics And Computer Technology Corporation | Correcting a defective metallization layer on an electronic component by polishing |
US5085015A (en) * | 1990-06-26 | 1992-02-04 | E. I. Du Pont De Nemours And Company | Process for improving the surface of liquid crystal polymers |
US5055158A (en) * | 1990-09-25 | 1991-10-08 | International Business Machines Corporation | Planarization of Josephson integrated circuit |
JP3362397B2 (ja) * | 1991-03-28 | 2003-01-07 | ソニー株式会社 | ポリッシュによる平坦化工程を含む電子装置の製造方法 |
US5137597A (en) * | 1991-04-11 | 1992-08-11 | Microelectronics And Computer Technology Corporation | Fabrication of metal pillars in an electronic component using polishing |
JP2833305B2 (ja) * | 1991-12-05 | 1998-12-09 | 富士通株式会社 | 半導体基板の製造方法 |
JP3141486B2 (ja) * | 1992-01-27 | 2001-03-05 | ソニー株式会社 | 半導体装置 |
US5314843A (en) * | 1992-03-27 | 1994-05-24 | Micron Technology, Inc. | Integrated circuit polishing method |
JP3060714B2 (ja) * | 1992-04-15 | 2000-07-10 | 日本電気株式会社 | 半導体集積回路の製造方法 |
US5334281A (en) * | 1992-04-30 | 1994-08-02 | International Business Machines Corporation | Method of forming thin silicon mesas having uniform thickness |
US5258318A (en) * | 1992-05-15 | 1993-11-02 | International Business Machines Corporation | Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon |
US5445996A (en) * | 1992-05-26 | 1995-08-29 | Kabushiki Kaisha Toshiba | Method for planarizing a semiconductor device having a amorphous layer |
US5264387A (en) * | 1992-10-27 | 1993-11-23 | International Business Machines Corporation | Method of forming uniformly thin, isolated silicon mesas on an insulating substrate |
US5234868A (en) * | 1992-10-29 | 1993-08-10 | International Business Machines Corporation | Method for determining planarization endpoint during chemical-mechanical polishing |
JPH07111962B2 (ja) * | 1992-11-27 | 1995-11-29 | 日本電気株式会社 | 選択平坦化ポリッシング方法 |
JPH06232141A (ja) * | 1992-12-07 | 1994-08-19 | Sony Corp | 半導体基板の作成方法及び固体撮像装置の製造方法 |
US5262346A (en) * | 1992-12-16 | 1993-11-16 | International Business Machines Corporation | Nitride polish stop for forming SOI wafers |
US5264395A (en) * | 1992-12-16 | 1993-11-23 | International Business Machines Corporation | Thin SOI layer for fully depleted field effect transistors |
US5318663A (en) * | 1992-12-23 | 1994-06-07 | International Business Machines Corporation | Method for thinning SOI films having improved thickness uniformity |
JP3139877B2 (ja) * | 1993-04-14 | 2001-03-05 | 株式会社東芝 | 半導体装置の製造装置およびその製造方法 |
US5433650A (en) * | 1993-05-03 | 1995-07-18 | Motorola, Inc. | Method for polishing a substrate |
US5310451A (en) * | 1993-08-19 | 1994-05-10 | International Business Machines Corporation | Method of forming an ultra-uniform silicon-on-insulator layer |
US5395801A (en) * | 1993-09-29 | 1995-03-07 | Micron Semiconductor, Inc. | Chemical-mechanical polishing processes of planarizing insulating layers |
US5422316A (en) * | 1994-03-18 | 1995-06-06 | Memc Electronic Materials, Inc. | Semiconductor wafer polisher and method |
US5668045A (en) * | 1994-11-30 | 1997-09-16 | Sibond, L.L.C. | Process for stripping outer edge of BESOI wafers |
US5494849A (en) * | 1995-03-23 | 1996-02-27 | Si Bond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator substrates |
US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
US6069081A (en) * | 1995-04-28 | 2000-05-30 | International Buiness Machines Corporation | Two-step chemical mechanical polish surface planarization technique |
JP3230986B2 (ja) * | 1995-11-13 | 2001-11-19 | 株式会社東芝 | ポリッシング方法、半導体装置の製造方法及び半導体製造装置。 |
JP3514908B2 (ja) * | 1995-11-13 | 2004-04-05 | 株式会社東芝 | 研磨剤 |
US5968239A (en) * | 1996-11-12 | 1999-10-19 | Kabushiki Kaisha Toshiba | Polishing slurry |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
JP3664987B2 (ja) * | 2001-03-14 | 2005-06-29 | シャープ株式会社 | 電子顕微鏡観察用試料の作成方法及び半導体装置の解析方法 |
US20020163072A1 (en) * | 2001-05-01 | 2002-11-07 | Subhash Gupta | Method for bonding wafers to produce stacked integrated circuits |
US7024756B2 (en) * | 2003-07-30 | 2006-04-11 | Hitachi Global Storage Technologies Netherlands, B.V. | Method of making a perpendicular recording magnetic head pole tip with an etchable adhesion CMP stop layer |
JP4238097B2 (ja) * | 2003-09-04 | 2009-03-11 | Tdk株式会社 | コイル部品の製造方法 |
JP4449076B2 (ja) * | 2004-04-16 | 2010-04-14 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7829464B2 (en) * | 2006-10-20 | 2010-11-09 | Spansion Llc | Planarization method using hybrid oxide and polysilicon CMP |
US7960247B2 (en) * | 2008-04-04 | 2011-06-14 | The Charles Stark Draper Laboratory, Inc. | Die thinning processes and structures |
US8017451B2 (en) | 2008-04-04 | 2011-09-13 | The Charles Stark Draper Laboratory, Inc. | Electronic modules and methods for forming the same |
US8273603B2 (en) * | 2008-04-04 | 2012-09-25 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
US8500515B2 (en) | 2010-03-12 | 2013-08-06 | Wayne O. Duescher | Fixed-spindle and floating-platen abrasive system using spherical mounts |
US8602842B2 (en) * | 2010-03-12 | 2013-12-10 | Wayne O. Duescher | Three-point fixed-spindle floating-platen abrasive system |
US8647171B2 (en) * | 2010-03-12 | 2014-02-11 | Wayne O. Duescher | Fixed-spindle floating-platen workpiece loader apparatus |
US8740668B2 (en) * | 2010-03-12 | 2014-06-03 | Wayne O. Duescher | Three-point spindle-supported floating abrasive platen |
US9806025B2 (en) | 2015-12-29 | 2017-10-31 | Globalfoundries Inc. | SOI wafers with buried dielectric layers to prevent Cu diffusion |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3009841A (en) * | 1959-03-06 | 1961-11-21 | Westinghouse Electric Corp | Preparation of semiconductor devices having uniform junctions |
US3386864A (en) * | 1963-12-09 | 1968-06-04 | Ibm | Semiconductor-metal-semiconductor structure |
US3740280A (en) * | 1971-05-14 | 1973-06-19 | Rca Corp | Method of making semiconductor device |
US3979237A (en) * | 1972-04-24 | 1976-09-07 | Harris Corporation | Device isolation in integrated circuits |
US3911562A (en) * | 1974-01-14 | 1975-10-14 | Signetics Corp | Method of chemical polishing of planar silicon structures having filled grooves therein |
US4037306A (en) * | 1975-10-02 | 1977-07-26 | Motorola, Inc. | Integrated circuit and method |
US4057939A (en) * | 1975-12-05 | 1977-11-15 | International Business Machines Corporation | Silicon wafer polishing |
JPS5534442A (en) * | 1978-08-31 | 1980-03-11 | Fujitsu Ltd | Preparation of semiconductor device |
IE52971B1 (en) * | 1979-07-23 | 1988-04-27 | Fujitsu Ltd | Method of manufacturing a semiconductor device wherein first and second layers are formed |
JPS57134961A (en) * | 1981-02-16 | 1982-08-20 | Nippon Telegr & Teleph Corp <Ntt> | Complementary type mis transistor device |
JPS5939044A (ja) * | 1982-08-26 | 1984-03-03 | Toko Inc | 絶縁分離集積回路用基板の製造方法 |
JPS5982746A (ja) * | 1982-11-04 | 1984-05-12 | Toshiba Corp | 半導体装置の電極配線方法 |
JPS59129439A (ja) * | 1983-01-14 | 1984-07-25 | Nec Corp | 半導体装置用基板の製造方法 |
JPS6054450A (ja) * | 1983-09-05 | 1985-03-28 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
JPS61120424A (ja) * | 1984-11-16 | 1986-06-07 | Oki Electric Ind Co Ltd | 誘電体分離基板の研磨方法 |
FR2582445B1 (fr) * | 1985-05-21 | 1988-04-08 | Efcis | Procede de fabrication de transistors mos a electrodes de siliciure metallique |
US4601779A (en) * | 1985-06-24 | 1986-07-22 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
-
1987
- 1987-03-30 US US07/031,809 patent/US4735679A/en not_active Expired - Lifetime
-
1988
- 1988-01-15 CA CA000556671A patent/CA1247259A/en not_active Expired
- 1988-01-18 JP JP63007091A patent/JP2661089B2/ja not_active Expired - Fee Related
- 1988-03-08 DE DE88103610T patent/DE3885637T2/de not_active Expired - Fee Related
- 1988-03-08 EP EP88103610A patent/EP0284840B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CA1247259A (en) | 1988-12-20 |
US4735679A (en) | 1988-04-05 |
EP0284840A3 (en) | 1990-10-31 |
DE3885637T2 (de) | 1994-05-11 |
EP0284840B1 (de) | 1993-11-18 |
JP2661089B2 (ja) | 1997-10-08 |
EP0284840A2 (de) | 1988-10-05 |
JPS63250853A (ja) | 1988-10-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |