DE3825547A1 - Verbindungsschicht auf eingegrabenem dielektrikum und verfahren zur herstellung einer solchen - Google Patents

Verbindungsschicht auf eingegrabenem dielektrikum und verfahren zur herstellung einer solchen

Info

Publication number
DE3825547A1
DE3825547A1 DE3825547A DE3825547A DE3825547A1 DE 3825547 A1 DE3825547 A1 DE 3825547A1 DE 3825547 A DE3825547 A DE 3825547A DE 3825547 A DE3825547 A DE 3825547A DE 3825547 A1 DE3825547 A1 DE 3825547A1
Authority
DE
Germany
Prior art keywords
oxide film
semiconductor substrate
connection
trenches
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3825547A
Other languages
German (de)
English (en)
Other versions
DE3825547C2 (enrdf_load_stackoverflow
Inventor
Takashi Urabe
Yoichi Tobita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to DE19883844719 priority Critical patent/DE3844719C2/de
Publication of DE3825547A1 publication Critical patent/DE3825547A1/de
Application granted granted Critical
Publication of DE3825547C2 publication Critical patent/DE3825547C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Semiconductor Memories (AREA)
DE3825547A 1987-09-08 1988-07-27 Verbindungsschicht auf eingegrabenem dielektrikum und verfahren zur herstellung einer solchen Granted DE3825547A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19883844719 DE3844719C2 (de) 1987-09-08 1988-07-27 Verbindungsschicht

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62225039A JPS6467945A (en) 1987-09-08 1987-09-08 Wiring layer formed on buried dielectric and manufacture thereof

Publications (2)

Publication Number Publication Date
DE3825547A1 true DE3825547A1 (de) 1989-03-16
DE3825547C2 DE3825547C2 (enrdf_load_stackoverflow) 1992-12-03

Family

ID=16823091

Family Applications (2)

Application Number Title Priority Date Filing Date
DE3825547A Granted DE3825547A1 (de) 1987-09-08 1988-07-27 Verbindungsschicht auf eingegrabenem dielektrikum und verfahren zur herstellung einer solchen
DE19883844719 Expired - Lifetime DE3844719C2 (de) 1987-09-08 1988-07-27 Verbindungsschicht

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE19883844719 Expired - Lifetime DE3844719C2 (de) 1987-09-08 1988-07-27 Verbindungsschicht

Country Status (4)

Country Link
US (1) US5041898A (enrdf_load_stackoverflow)
JP (1) JPS6467945A (enrdf_load_stackoverflow)
KR (1) KR940008358B1 (enrdf_load_stackoverflow)
DE (2) DE3825547A1 (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10041691A1 (de) * 2000-08-24 2002-03-14 Infineon Technologies Ag Halbleiteranordnung
DE10051909A1 (de) * 2000-10-19 2002-05-16 Infineon Technologies Ag Randabschluss für Hochvolt-Halbleiterbauelement und Verfahren zum Herstellen eines Isolatorgebietes in einem Halbleiterkörper für solchen Randabschluss

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516720A (en) * 1994-02-14 1996-05-14 United Microelectronics Corporation Stress relaxation in dielectric before metallization
KR100236097B1 (ko) * 1996-10-30 1999-12-15 김영환 반도체 장치의 격리막 형성방법
US6306727B1 (en) * 1997-08-18 2001-10-23 Micron Technology, Inc. Advanced isolation process for large memory arrays
US6451655B1 (en) * 1999-08-26 2002-09-17 Stmicroelectronics S.R.L. Electronic power device monolithically integrated on a semiconductor and comprising a first power region and at least a second region as well as an isolation structure of limited planar dimension
DE10242661A1 (de) * 2002-09-13 2004-03-25 Conti Temic Microelectronic Gmbh Verfahren zum Herstellen von Isolationsstrukturen
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7247570B2 (en) * 2004-08-19 2007-07-24 Micron Technology, Inc. Silicon pillars for vertical transistors
US7285812B2 (en) * 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7199419B2 (en) * 2004-12-13 2007-04-03 Micron Technology, Inc. Memory structure for reduced floating body effect
US7229895B2 (en) * 2005-01-14 2007-06-12 Micron Technology, Inc Memory array buried digit line
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
KR100703042B1 (ko) * 2006-09-08 2007-04-09 (주)에이펙스 검사용 프로브 기판 및 그 제조 방법
KR100703043B1 (ko) * 2006-09-21 2007-04-09 (주)에이펙스 검사용 프로브 기판 및 그 제조 방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
IT1397603B1 (it) * 2009-12-21 2013-01-16 St Microelectronics Srl Trincee di isolamento per strati semiconduttori.
US9401363B2 (en) 2011-08-23 2016-07-26 Micron Technology, Inc. Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2949360A1 (de) * 1978-12-08 1980-06-26 Hitachi Ltd Verfahren zur herstellung einer oxidierten isolation fuer integrierte schaltungen
EP0036764A2 (en) * 1980-03-25 1981-09-30 Fujitsu Limited A semiconductor device with a V-groove insulating isolation structure and a method of manufacturing such a device
EP0086915A2 (en) * 1981-11-20 1983-08-31 Fujitsu Limited Semiconductor device having conductor lines connecting the elements
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58200554A (ja) * 1982-05-19 1983-11-22 Hitachi Ltd 半導体装置の製造方法
US4819054A (en) * 1982-09-29 1989-04-04 Hitachi, Ltd. Semiconductor IC with dual groove isolation
US4910575A (en) * 1986-06-16 1990-03-20 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2949360A1 (de) * 1978-12-08 1980-06-26 Hitachi Ltd Verfahren zur herstellung einer oxidierten isolation fuer integrierte schaltungen
EP0036764A2 (en) * 1980-03-25 1981-09-30 Fujitsu Limited A semiconductor device with a V-groove insulating isolation structure and a method of manufacturing such a device
EP0086915A2 (en) * 1981-11-20 1983-08-31 Fujitsu Limited Semiconductor device having conductor lines connecting the elements
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Malaviya, S.D.: Deep Dielectric Isolation. In: IBM TDB, Bd. 26, Nr. 7A, Dezember 1983, S. 3188-3189 *
Thiel, K.P. et.al.: Polyimide Nitride Isolation. In: IBM TDB, Bd. 27, Nr. 7B, Dezember 1984, S. 4139-4140 *
Yamabe, Kikuo und Imai, Keitaro: Nonplanar Oxidation. In: IEEE Transactions on Electron Devices, Bd. ED-34, Nr. 8, August 1987, S. 1681-1687 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10041691A1 (de) * 2000-08-24 2002-03-14 Infineon Technologies Ag Halbleiteranordnung
US6838746B2 (en) 2000-08-24 2005-01-04 Infineon Technologies Ag Semiconductor configuration and method for fabricating the configuration
EP1312115B1 (de) * 2000-08-24 2009-05-20 Infineon Technologies AG Halbleiteranordnung und verfahren zu dessen herstellung
DE10051909A1 (de) * 2000-10-19 2002-05-16 Infineon Technologies Ag Randabschluss für Hochvolt-Halbleiterbauelement und Verfahren zum Herstellen eines Isolatorgebietes in einem Halbleiterkörper für solchen Randabschluss
DE10051909B4 (de) * 2000-10-19 2007-03-22 Infineon Technologies Ag Randabschluss für Hochvolt-Halbleiterbauelement und Verfahren zum Herstellen eines Isolationstrenches in einem Halbleiterkörper für solchen Randabschluss

Also Published As

Publication number Publication date
DE3844719C2 (de) 1995-06-14
JPS6467945A (en) 1989-03-14
KR890005844A (ko) 1989-05-17
US5041898A (en) 1991-08-20
KR940008358B1 (ko) 1994-09-12
DE3825547C2 (enrdf_load_stackoverflow) 1992-12-03

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