DE3780492T2 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3780492T2
DE3780492T2 DE8787104103T DE3780492T DE3780492T2 DE 3780492 T2 DE3780492 T2 DE 3780492T2 DE 8787104103 T DE8787104103 T DE 8787104103T DE 3780492 T DE3780492 T DE 3780492T DE 3780492 T2 DE3780492 T2 DE 3780492T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787104103T
Other languages
English (en)
Other versions
DE3780492D1 (de
Inventor
Atsushi Suzuki
Hideo Itoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3780492D1 publication Critical patent/DE3780492D1/de
Publication of DE3780492T2 publication Critical patent/DE3780492T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE8787104103T 1986-03-20 1987-03-20 Halbleiterspeicheranordnung. Expired - Fee Related DE3780492T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6460586A JP2559028B2 (ja) 1986-03-20 1986-03-20 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3780492D1 DE3780492D1 (de) 1992-08-27
DE3780492T2 true DE3780492T2 (de) 1993-03-11

Family

ID=13263052

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787104103T Expired - Fee Related DE3780492T2 (de) 1986-03-20 1987-03-20 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4829477A (de)
EP (1) EP0239021B1 (de)
JP (1) JP2559028B2 (de)
KR (1) KR940000147B1 (de)
DE (1) DE3780492T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4951252A (en) * 1988-10-25 1990-08-21 Texas Instruments Incorporated Digital memory system
US4939693A (en) * 1989-02-14 1990-07-03 Texas Instruments Incorporated BiCMOS static memory with improved performance stability
KR900019011A (ko) * 1989-05-16 1990-12-22 김광호 반도체 메모리장치의 라이트 드라이버
US4985864A (en) * 1989-06-23 1991-01-15 Vlsi Technology, Inc. Static random access memory having column decoded bit line bias
JP2582439B2 (ja) * 1989-07-11 1997-02-19 富士通株式会社 書き込み可能な半導体記憶装置
JPH03176890A (ja) * 1989-12-04 1991-07-31 Toshiba Corp 複数ポート半導体メモリ
EP0446847B1 (de) * 1990-03-12 1998-06-17 Nec Corporation Halbleiterspeicheranordnung mit einem verbesserten Schreibmodus
JP2869260B2 (ja) * 1992-08-25 1999-03-10 シャープ株式会社 半導体記憶装置
KR100699406B1 (ko) * 2006-01-23 2007-03-23 삼성전자주식회사 기입 회복 시간 제어회로 및 그 제어방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967252A (en) * 1974-10-03 1976-06-29 Mostek Corporation Sense AMP for random access memory
JPS5589980A (en) * 1978-11-27 1980-07-08 Nec Corp Semiconductor memory unit
JPS5951072B2 (ja) * 1979-02-26 1984-12-12 日本電気株式会社 半導体メモリ装置
JPS55129994A (en) * 1979-03-26 1980-10-08 Nec Corp Semiconductor memory device
JPS59178685A (ja) * 1983-03-30 1984-10-09 Toshiba Corp 半導体記憶回路
JPS6258486A (ja) * 1985-09-06 1987-03-14 Nippon Telegr & Teleph Corp <Ntt> ＢｉＣＭＯＳメモリ回路

Also Published As

Publication number Publication date
KR940000147B1 (ko) 1994-01-07
JPS62222489A (ja) 1987-09-30
DE3780492D1 (de) 1992-08-27
EP0239021A2 (de) 1987-09-30
KR870009388A (ko) 1987-10-26
US4829477A (en) 1989-05-09
EP0239021B1 (de) 1992-07-22
JP2559028B2 (ja) 1996-11-27
EP0239021A3 (en) 1989-07-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee