DE3750002D1 - Statischer Direktzugriffspeicher einer Bi-CMOS-Konstruktion. - Google Patents

Statischer Direktzugriffspeicher einer Bi-CMOS-Konstruktion.

Info

Publication number
DE3750002D1
DE3750002D1 DE3750002T DE3750002T DE3750002D1 DE 3750002 D1 DE3750002 D1 DE 3750002D1 DE 3750002 T DE3750002 T DE 3750002T DE 3750002 T DE3750002 T DE 3750002T DE 3750002 D1 DE3750002 D1 DE 3750002D1
Authority
DE
Germany
Prior art keywords
random access
access memory
static random
cmos construction
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3750002T
Other languages
English (en)
Other versions
DE3750002T2 (de
Inventor
Hiroshi C O Nec Corporat Shiba
Shoji C O Nec Corporati Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP61191323A external-priority patent/JPS6348694A/ja
Priority claimed from JP61191322A external-priority patent/JPS6348695A/ja
Priority claimed from JP61191321A external-priority patent/JPS6348693A/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3750002D1 publication Critical patent/DE3750002D1/de
Application granted granted Critical
Publication of DE3750002T2 publication Critical patent/DE3750002T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
DE3750002T 1986-08-15 1987-08-14 Statischer Direktzugriffspeicher einer Bi-CMOS-Konstruktion. Expired - Fee Related DE3750002T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP61191323A JPS6348694A (ja) 1986-08-15 1986-08-15 半導体メモリ
JP61191322A JPS6348695A (ja) 1986-08-15 1986-08-15 半導体メモリ
JP61191321A JPS6348693A (ja) 1986-08-15 1986-08-15 半導体メモリ

Publications (2)

Publication Number Publication Date
DE3750002D1 true DE3750002D1 (de) 1994-07-14
DE3750002T2 DE3750002T2 (de) 1995-01-12

Family

ID=27326466

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3750002T Expired - Fee Related DE3750002T2 (de) 1986-08-15 1987-08-14 Statischer Direktzugriffspeicher einer Bi-CMOS-Konstruktion.

Country Status (3)

Country Link
US (1) US4839862A (de)
EP (2) EP0258715B1 (de)
DE (1) DE3750002T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075885A (en) * 1988-12-21 1991-12-24 National Semiconductor Corporation Ecl eprom with cmos programming
US4933899A (en) * 1989-02-01 1990-06-12 Cypress Semiconductor Bi-CMOS semiconductor memory cell
US4939693A (en) * 1989-02-14 1990-07-03 Texas Instruments Incorporated BiCMOS static memory with improved performance stability
JP2601903B2 (ja) * 1989-04-25 1997-04-23 株式会社東芝 半導体記憶装置
JPH03116488A (ja) * 1989-09-29 1991-05-17 Fujitsu Ltd 半導体記憶装置
JP2501930B2 (ja) * 1990-02-26 1996-05-29 株式会社東芝 半導体集積回路
DE69015371T2 (de) * 1990-05-17 1995-07-13 Ibm Lese-/schreibe-/wiederherstellungsschaltung für speichermatrizen.
US5222039A (en) * 1990-11-28 1993-06-22 Thunderbird Technologies, Inc. Static random access memory (SRAM) including Fermi-threshold field effect transistors
US5257227A (en) * 1991-01-11 1993-10-26 International Business Machines Corp. Bipolar FET read-write circuit for memory
EP0593152B1 (de) * 1992-10-14 2000-12-27 Sun Microsystems, Inc. Direktzugriffspeicherentwurf
JPH06349281A (ja) * 1993-06-04 1994-12-22 Fujitsu Ltd 半導体装置
KR100292640B1 (ko) * 1995-04-05 2001-06-15 로데릭 더블류 루이스 계층적비트라인구조를갖는메모리회로
US5600602A (en) * 1995-04-05 1997-02-04 Micron Technology, Inc. Hierarchical memory array structure having electrically isolated bit lines for temporary data storage
TW372363B (en) * 1996-04-04 1999-10-21 Mitsubishi Electric Corp Manufacturing method for static semiconductor memory apparatus and semiconductor apparatus and bipolar transistor
JP2865078B2 (ja) * 1996-10-02 1999-03-08 日本電気株式会社 半導体記憶装置
US6011711A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. SRAM cell with p-channel pull-up sources connected to bit lines
JP3860403B2 (ja) * 2000-09-25 2006-12-20 株式会社東芝 半導体メモリ装置
US7050323B2 (en) * 2002-08-29 2006-05-23 Texas Instruments Incorporated Ferroelectric memory
US7440335B2 (en) * 2006-05-23 2008-10-21 Freescale Semiconductor, Inc. Contention-free hierarchical bit line in embedded memory and method thereof
US7719905B2 (en) * 2007-05-17 2010-05-18 Hynix Semiconductor, Inc. Semiconductor memory device
US8593860B2 (en) 2011-12-09 2013-11-26 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays
US8693236B2 (en) * 2011-12-09 2014-04-08 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6032912B2 (ja) * 1979-09-13 1985-07-31 株式会社東芝 Ｃｍｏｓセンスアンプ回路
JPH0648595B2 (ja) * 1982-08-20 1994-06-22 株式会社東芝 半導体記憶装置のセンスアンプ
JPS59151386A (ja) * 1983-01-31 1984-08-29 Fujitsu Ltd 半導体記憶装置
EP0121394B1 (de) * 1983-03-28 1991-10-23 Fujitsu Limited Statisches Halbleiterspeichergerät mit eingebauten Redundanzspeicherzellen
KR900005667B1 (ko) * 1984-11-20 1990-08-03 후지쓰 가부시끼가이샤 반도체 기억장치
JPH0785358B2 (ja) * 1984-12-17 1995-09-13 株式会社日立製作所 半導体記憶装置

Also Published As

Publication number Publication date
EP0258715A3 (en) 1990-07-04
EP0258715B1 (de) 1994-06-08
EP0523756A2 (de) 1993-01-20
EP0523756A3 (en) 1993-06-09
DE3750002T2 (de) 1995-01-12
US4839862A (en) 1989-06-13
EP0258715A2 (de) 1988-03-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee