EP0121394B1 - Statisches Halbleiterspeichergerät mit eingebauten Redundanzspeicherzellen - Google Patents

Statisches Halbleiterspeichergerät mit eingebauten Redundanzspeicherzellen Download PDF

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Publication number
EP0121394B1
EP0121394B1 EP19840302044 EP84302044A EP0121394B1 EP 0121394 B1 EP0121394 B1 EP 0121394B1 EP 19840302044 EP19840302044 EP 19840302044 EP 84302044 A EP84302044 A EP 84302044A EP 0121394 B1 EP0121394 B1 EP 0121394B1
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Prior art keywords
selecting line
memory cell
power supply
line means
memory cells
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Expired - Lifetime
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EP19840302044
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English (en)
French (fr)
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EP0121394A3 (en
EP0121394A2 (de
Inventor
Keizo Aoyama
Teruo Dai-2 Yayoi-So 5 Seki
Takahiko Yamauchi
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Fujitsu Ltd
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Fujitsu Ltd
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Priority claimed from JP58050347A external-priority patent/JPH0652639B2/ja
Priority claimed from JP58051535A external-priority patent/JPS59178691A/ja
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Publication of EP0121394A3 publication Critical patent/EP0121394A3/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Definitions

  • the present invention relates to a static semiconductor memory device incorporating redundancy memory cells.
  • a large number of memory cells are arranged along rows and columns.
  • the density of defects generated in such a semiconductor memory device during the manufacture thereof is relatively independent of the integration density of the device. Rather, it derives from the semiconductor manufacturing technology. In general, the higher the integration density of the device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of a semiconductor memory device.
  • redundancy memory cells To overcome the problem of defective memory cells, use is made of redundancy (redundant) memory cells.
  • a redundancy memory cell row or column is selected instead of the memory cell row or column including the defective memory cell.
  • one or two redundancy memory cell rows or columns are usually provided.
  • a problem in the prior art has been that when the defective memory cell has a direct current (DC) defect, i.e., when the defective memory cell is short-circuited, the DC defect itself is not resolved even when a redundancy memory cell row or column is selected.
  • DC direct current
  • An article by Ochii et al in the same journal, pp 798-803, discloses an ultralow power 64 k bit CMOS RAM having spare rows and columns of memory cells.
  • the spare rows or columns are again selected by programming fuses, and in addition, fuses are provided for isolating a failure row electrically by cutting the corresponding power line.
  • this necessitates replacing both a failure row and its neighbour by a pair of spare rows so as to complete the power isolation. This is wasteful of spare cell capacity.
  • a static semiconductor memory device comprising: a power supply means; a memory cell array having a plurality of normal memory cell rows or columns each comprising a plurality of memory cells; at least one redundancy (redundant) memory cell row or column comprising a plurality of redundancy memory cells, said redundancy memory cell row or column being able to replace one of said normal cell rows or columns including a defective cell; a plurality of selecting line means, each connected to one of said normal memory cell rows or columns, or to a said redundancy memory cell row or column; and connecting/disconnecting means to/from said redundancy memory cell row or column each linked between the corresponding selecting line means and said power supply means; and characterised by: a plurality of connecting/disconnecting means, each linked between one of said selecting line means and said power supply means and operable to temporarily electrically disconnect said selecting line means from said power supply means for at least a non-selected mode of said device, during normal operation thereof; wherein said connecting/dis
  • the potential of a clock signal is applied to loads linked between bit line pairs and a power supply at least during a non-selected state (stand-by state) so as to cut off currents flowing through the loads, thereby reducing the load current of bit lines for all memory cells, including a defective memory cell. That is, even when the defective memory cell has a DC defect, power supply currents due to the DC defect are suppressed thereby substantially resolving the DC defect.
  • Fig. 1 which illustrates a prior art static semiconductor memory device
  • Each memory cell is connected to one word line, a hold line and a pair of bit lines.
  • a memory cell C00 is connected to a word line W0 , to a hold line H0 , and to bit lines B0 and B 0.
  • a series of memory cells C 0R , C 1R , ..., C n-1,R are arranged along the column direction. These memory cells C 0R , C 1R , ..., C n-1,R serve as redundancy memory cells.
  • the hold lines H0 , H1 , ..., H n-1 are connected to earth, which serves as one of the power supplies.
  • the bit lines B0 , B 0 , B1 , B 1 , ..., B n-1 , B n-1 , B R , and B R are connected via load transistors Q L0 , Q L0 , Q L1 , Q L1 , ..., Q LR , Q LR to a power supply V CC .
  • the load transistors are, for example, enhancement metal-insulator-semiconductor (MIS) transistors.
  • Reference CD1 designates column decoders
  • CD2 designates a decoder for selecting the redundancy memory cells.
  • the decoder CD2 is comprised of a resistor R, fuses F X , F0 , F 0 , F1 , F 1 , ..., F n-1 , F n-1 , and transistors Q X0 , Q X1 , ..., Q Xn-1 .
  • SA is a sense amplifier
  • OB is an output buffer
  • D out is output data
  • A0', A0 ', A1', A 1', ..., A l-1 , and A l-1 ' are column address signals.
  • the redundancy memory cell C 0R instead of the defective memory cell C00 is actually selected by the fuse F0'. Note, if no defective memory cell is detected, none of the fuses are melted, and, accordingly, all the fuses are in a connected state. Thus, it is possible to detect (select) a redundancy memory cell instead of a defective memory cell.
  • the memory cell C00 is comprised of resistors R1 and R2 , driver transistors Q1 and Q2 , and transfer transistors Q3 and Q4. Therefore, when a DC defect is generated so as to short-circuit the bit line B0 or B 0 to the hold line H0 , a current flows from the power supply V CC via the load transistor Q L and the short-circuited portion to the hold line H0 even when the redundancy memory cell C 0R is selected instead of the memory cell C00. Therefore, the DC defect itself is not resolved.
  • a clock signal ⁇ is applied to the gates of the transistors Q L0 , Q L0 , Q L1 , Q L1 , ..., Q L,n-1 , Q L,n-1 , Q LR , Q LR .
  • the potential of the clock signal ⁇ is made low at least during a non-selected state, thereby preventing currents from flowing from the power supply V CC to all the memory cells.
  • the above-mentioned clock signal (pulse signal) ⁇ is obtained as an inversion signal of a chip select signal CS . That is, the clock signal ⁇ is easily obtained by using an inverter G0 as shown in Fig. 5.
  • the potential of the clock signal ⁇ is, in this case, low, so that all the load transistors are cut off.
  • a current flowing through the defective portion in the case of the potential of the clock signal ⁇ being high is extremely small as compared with the total power consumption of the semiconductor device.
  • Figures 6A, 6B, and 6C are also timing diagrams for explaining the generation of the clock signal ⁇ of Fig. 3.
  • the clock signal ⁇ as shown in Fig. 6C becomes high for a definite (short) time period only after the chip select signal CS as shown in Fig. 6A is changed or after one ADD of the row address signals A0 , A1 , ..., and A l-1 is changed. Therefore, the current flowing from the power supply V CC to the above-mentioned defective portion is of shorter duration than with the signal ⁇ as shown in Fig. 4B.
  • the clock signal ⁇ as shown in Fig. 6C can be obtained by a pulse generating circuit PG of Fig. 7. That is, in Fig. 7, the pulse generating circuit PG comprises a plurality of clock pulse generating circuits PG0 , PG1 , ..., PG l-1 , and PG l corresponding to each of the row address signals A0 , A1 , ..., A l-1 , and the chip select signal CS . Therefore, when one of the signals A0 , A1 , ..., A l-1 , and CS is changed, for example, when the signal A0 is changed, the clock pulse generating circuit PG0 generates the clock signal ⁇ via an OR circuit OR. That is, when the device of Fig. 3 is changed from a non-selected state to a selected state or vice versa, or when the selected row is changed, the pulse generating circuit PG generates the clock signal ⁇ .
  • Fig. 8 which is a detailed logic circuit diagram of one of the clock pulse generating circuits PG i of the pulse generating circuit PG of Fig. 7, references G1 to G4 are NAND gates, G5 and G6 NOR gates, G7 an OR gate, and C1 and C2 capacitors. Operation will be explained below with reference to Figs. 9A to 9H.
  • the address signal A i node a
  • the output b of the NAND gate G1 changes as shown in Fig. 9B
  • the output d of the NAND gate G2 is an inverted signal of the signal b which is delayed a little by the capacitor C1 , as shown in Fig. 9D.
  • the output f of the NOR gate G5 is a pulse which is generated by the rise of the address signal A i , as shown in Fig. 9E.
  • the output g of the NOR gate G6 is a signal which is generated by the fall of the address signal A i , as shown in Fig. 9G. Therefore, as shown in Fig. 9H the output CP i of the OR gate G7 , which combines the signal f with the signal g, is a clock signal which is generated by the change of the address signal A0 , A1 , ..., A l-1 , or the signal CS .
  • the bit line load currents are reduced in duration, the power supply currents flowing through a defective memory cell can be reduced, even when the defective memory cell has a DC defect. Therefore, the DC defect can be substantially resolved.
  • fuses F10, F 10 , F11 , F 11 , ..., F 1,n-1 , F 1,n-1 , F 1R , and F 1R are added to the elements of Fig. 1.
  • Each fuse is provided between the memory cells and the power supply V CC .
  • each fuse can be provided on the drain side of the load transistor (between drain and V cc )as well as on the source side (between source and bit line) thereof. In either case, the same effect is exhibited.
  • the fuses F X , F0 , F1' , ..., and F n-1 ' are melted in the same way as stated above.
  • the fuses F10 and F 10 are melted. Therefore, even when the memory cell C00 has a DC defect, no current flows from the power supply V CC via the memory cell C00 to the hold line H0. This means that the DC defect is completely resolved.
  • fuses F20 , F21 , ..., F 2,n-1 , and F 2R are added to the elements of Fig. 1. This case is equivalent to that wherein each fuse is provided between the memory cells and the power supply V CC .
  • the fuses F X , F0 , F1' , ..., and F n-1 ' are melted in the same way as stated above.
  • the fuse F20 is melted, thereby producing the same result as in the Fig. 10 device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Claims (6)

  1. Statische Halbleiterspeichervorrichtung mit:
       einer Energieversorgungseinrichtung (VCC);
       einem Speicherzellenarray, das eine Vielzahl von normalen Speicherzellenreihen- oder -spalten (Cij; 0≦ i, j ≦ n-1) hat, wenigstens einer (redundanten) RedundanzSpeicherzellenreihe oder -spalte, die eine Vielzahl von Redundanzspeicherzellen (C0R, C1R, ..., Cn-1, R) umfaßt, welche Redundanzspeicherzellenreihe oder -spalte eine der genannten normalen Zellenreihen oder -spalten ersetzen kann, die eine defekte Zelle enthält;
       einer Vielzahl von Auswahlleitungseinrichtungen (B₀, B₀; B₁, B₁; ...; Bn-1, B n-1); BR, B R), die jeweils mit einer der genannten Speicherzellenreihen oder -spalten oder mit einer genannten Redundanzspeicherzellenreihe oder -spalte verbunden sind; und
       Verbindungs/Trenn-Einrichtungen (QLR, QL ​ R ¯
    Figure imgb0005
    ) zu/von der genannten Redundanzspeicherzellenreihe oder -spalte, die jeweils zwischen Auswahlleitungseinrichtungen (BR, B R) und der genannten Energieversorgungseinrichtung (VCC) verbunden sind;
       einer Vielzahl von Verbindungs/Trenn-Einrichtungen (QL0, Q L0; QL1, Q L1; ... QL,n-1; Q L,n-1) zu/von den genannten normalen Speicherzellenreihen oder -spalten, die jeweils zwischen einer der genannten Auswahlleitungseinrichtungen (B₀, B₀; ...; Bn-1, B n-1) und der genannten Energieversorgungseinrichtung (VCC) verbunden und betreibbar sind, um temporär die genannte Auswahlleitungseinrichtung (B₀, B₀; ...; Bn-1, B n-1) von der genannten Energieversorgungseinrichtung (VCC) zu trennen, für wenigstens einen nicht-ausgewählten Modus der genannten statischen Halbleiterspeichervorrichtung, während des normalen Betriebs derselben;
       bei der die genannte Verbindungs/Trenn-Einrichtungen (QL0, Q L0; ... QL,n-1; Q L,n-1) Transistoren umfassen, die zwischen der genannten Auswahlleitungseinrichtung (B₀, B₀; ...; Bn-1, B n-1) und der genannten Energiever- sorgungseinrichtung (VCC) verbunden sind, wobei jeder der genannten Transistoren ein Anreicherungs-MIS-Transistor ist, der ein Drain hat, das mit der genannten Energieversorgungseinrichtung (VCC) verbunden ist, eine Source, die mit einer der genannten Auswahlleitungseinrichtungen verbunden ist, und ein Gate, wobei das Potential des genannten Gate durch die genannten Puls-(ø)-Erzeugungsschaltungen (PGi; i = 0 ... ℓ) gesteuert wird, die jedem der Reihenadreßsignale (Ai; i = 0 ... ℓ-1) und einem invertierten Chip-Auswahlsignal (CS) entsprechen, um so den genannten MIS-Transistor ein- und auszuschalten.
  2. Vorrichtung nach Anspruch 1, ferner mit einer Vielzahl von zusätzlichen Auswahlleitungseinrichtungen (W₀, W₁, ... Wn-1), die mit den genannten Speicherzellen und den genannten Redundanzspeicherzellen verbunden sind, wobei die genannte zusätzliche Auswahlleitungseinrichtung senkrecht zu der genannten Auswahlleitungseinrichtung (B₀, B₀; ...; Bn-1, B n-1, BR, B R) ist.
  3. Vorrichtung nach Anspruch 2, bei der die genannte Verbindungs/Trenn-Einrichtung (QL0, Q L0; ... QL,n-1; Q L,n-1) die genannte Auwahlleitungseinrichtung (B₀, B₀; ...; Bn-1, B n-1) mit der genannten Energieversorgungseinrichtung (VCC) verbindet, für eine definierte Zeitperiode nachdem die genannte statische Halbleiterspeichervorrichtung von einem nicht-ausgewählten Modus in einen ausgewählten Modus wechselt, oder nachdem das Potential von einer der genannten zusätzlichen Auswahlleitungseinrichtungen (W₀, W₁, ..., Wn-1) geändert worden ist.
  4. Vorrichtung nach Anspruch 1, 2 oder 3, bei der die genannte Verbindungs/Trenn-Einrichtung (QL0, Q L0; ... QL,n-1; Q L,n-1, QLR, Q LR) ferner umfaßt:
       Schmelzeinsätze (F₁₀, F₁₀, ... F₁, n-1, F₁, ​ n ¯ -1
    Figure imgb0006
    , F1R, F 1R), die zwischen den genannten Auswahlleitungseinrichtungen und den genannten Transistoren verbunden sind; und
       eine Schmelzeinrichtung zum Schmelzen der genannten Schmelzeinsätze, die mit einer der genannten Auswahlleitungseinrichtungen (B₀, B₀, ..., Bn-1, B n-1) verbindbar sind, die mit einer oder mehreren defekten Speicherzellen verbunden sind.
  5. Vorrichtung nach Anspruch 1, 2 oder 3, bei der die genannten Verbindungs/Trenn-Einrichtungen(QL0, Q L0; ... QL,n-1; Q L,n-1, QLR, Q LR) ferner umfassen:
       Schmelzeinsätze (F₂₀, F₂₁, ...F2, n-1, F2R), die zwischen der genannten Energieversorgungseinrichtung (VCC) und den genannten Transistoren verbunden sind; und
       eine Schmelzeinrichtung zum Schmelzen der genannten Schmelzeinsätze, die mit einer der genannten Auswahleinrichtungen (B₀, B₀, ..., Bn-1, B n-1) verbindbar sind, die mit einer oder mehreren defekten Speicherzellen verbunden ist.
  6. Vorrichtung nach einem der vorhergehenden Ansprüche, bei der jede der genannten Auswahlleitungseinrichtungen (B₀, B₀; B₁, B₁;... Bn-1, B n-1; BR, B R) ein Paar von Bitleitungen umfaßt.
EP19840302044 1983-03-28 1984-03-27 Statisches Halbleiterspeichergerät mit eingebauten Redundanzspeicherzellen Expired - Lifetime EP0121394B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP58050347A JPH0652639B2 (ja) 1983-03-28 1983-03-28 半導体記憶装置
JP50347/83 1983-03-28
JP58051535A JPS59178691A (ja) 1983-03-29 1983-03-29 半導体記憶装置
JP51535/83 1983-03-29

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EP0121394A3 EP0121394A3 (en) 1988-01-27
EP0121394B1 true EP0121394B1 (de) 1991-10-23

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JP3115623B2 (ja) * 1991-02-25 2000-12-11 株式会社日立製作所 スタティック型ｒａｍ
JP2888034B2 (ja) * 1991-06-27 1999-05-10 日本電気株式会社 半導体メモリ装置
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US5768206A (en) * 1995-06-07 1998-06-16 Sgs-Thomson Microelectronics, Inc. Circuit and method for biasing bit lines
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US7117400B2 (en) * 2002-11-13 2006-10-03 International Business Machines Corporation Memory device with data line steering and bitline redundancy
TWI242213B (en) * 2003-09-09 2005-10-21 Winbond Electronics Corp Device and method of leakage current cuter and memory cell and memory device thereof
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EP0121394A3 (en) 1988-01-27
EP0121394A2 (de) 1984-10-10
US4587639A (en) 1986-05-06
DE3485188D1 (de) 1991-11-28

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