DE3579977D1 - Methode zum entwurf logisch integrierter schaltungen. - Google Patents

Methode zum entwurf logisch integrierter schaltungen.

Info

Publication number
DE3579977D1
DE3579977D1 DE8585305307T DE3579977T DE3579977D1 DE 3579977 D1 DE3579977 D1 DE 3579977D1 DE 8585305307 T DE8585305307 T DE 8585305307T DE 3579977 T DE3579977 T DE 3579977T DE 3579977 D1 DE3579977 D1 DE 3579977D1
Authority
DE
Germany
Prior art keywords
designing
integrated circuits
logically integrated
logically
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585305307T
Other languages
English (en)
Inventor
Hideo Kikuchi
Sadao Tsutsumi
Akira Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3579977D1 publication Critical patent/DE3579977D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8585305307T 1984-07-25 1985-07-25 Methode zum entwurf logisch integrierter schaltungen. Expired - Fee Related DE3579977D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59154665A JPS6156435A (ja) 1984-07-25 1984-07-25 半導体集積回路装置に於ける配線長予測方法

Publications (1)

Publication Number Publication Date
DE3579977D1 true DE3579977D1 (de) 1990-11-08

Family

ID=15589211

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585305307T Expired - Fee Related DE3579977D1 (de) 1984-07-25 1985-07-25 Methode zum entwurf logisch integrierter schaltungen.

Country Status (5)

Country Link
US (1) US4823278A (de)
EP (1) EP0170501B1 (de)
JP (1) JPS6156435A (de)
KR (1) KR900000176B1 (de)
DE (1) DE3579977D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0640340B2 (ja) * 1986-07-31 1994-05-25 株式会社日立製作所 データ表示装置
US5124273A (en) * 1988-06-30 1992-06-23 Kabushiki Kaisha Toshiba Automatic wiring method for semiconductor integrated circuit devices
US5239465A (en) * 1988-10-11 1993-08-24 Hitachi, Ltd. Method and system for layout design of integrated circuits with a data transferring flow
JP2664465B2 (ja) * 1989-03-15 1997-10-15 富士通株式会社 半導体装置のセル配置方法
JP2746762B2 (ja) * 1990-02-01 1998-05-06 松下電子工業株式会社 半導体集積回路のレイアウト方法
US5235521A (en) * 1990-03-30 1993-08-10 International Business Machines Corporation Reducing clock skew in large-scale integrated circuits
US5077676A (en) * 1990-03-30 1991-12-31 International Business Machines Corporation Reducing clock skew in large-scale integrated circuits
US5218551A (en) * 1990-04-30 1993-06-08 International Business Machines Corporation Timing driven placement
US5189629A (en) * 1990-06-06 1993-02-23 Hughes Aircraft Company Method of logic gate reduction in a logic gate array
US5367469A (en) * 1990-12-13 1994-11-22 Vlsi Technology, Inc. Predictive capacitance layout method for integrated circuits
US5197015A (en) * 1990-12-20 1993-03-23 Vlsi Technology, Inc. System and method for setting capacitive constraints on synthesized logic circuits
JPH0582611A (ja) * 1991-09-02 1993-04-02 Rohm Co Ltd 論理回路のレイアウトパターン検証方法
US5452224A (en) * 1992-08-07 1995-09-19 Hughes Aircraft Company Method of computing multi-conductor parasitic capacitances for VLSI circuits
US5490083A (en) * 1992-10-05 1996-02-06 Matsushita Electric Industrial Co., Ltd. Method and apparatus for classifying and evaluating logic circuit
JP2763721B2 (ja) * 1992-12-18 1998-06-11 川崎製鉄株式会社 論理回路検証方法
US5596505A (en) * 1993-07-23 1997-01-21 Vlsi Technology, Inc. Estimation of pin-to-pin timing for compiled blocks
JPH07129647A (ja) * 1993-11-01 1995-05-19 Nec Corp Ｃａｄシステム
JP2758817B2 (ja) * 1993-12-13 1998-05-28 日本電気株式会社 論理回路実現性判定システム
US6181162B1 (en) 1994-04-10 2001-01-30 Altera Corporation Programmable logic device with highly routable interconnect
US6294928B1 (en) 1996-04-05 2001-09-25 Altera Corporation Programmable logic device with highly routable interconnect
US5761080A (en) * 1995-11-22 1998-06-02 International Business Machines Corporation Method and apparatus for modeling capacitance in an integrated circuit
JPH1092938A (ja) * 1996-09-10 1998-04-10 Fujitsu Ltd レイアウト方法、レイアウト装置、及び、データベース
US6148432A (en) * 1997-11-17 2000-11-14 Micron Technology, Inc. Inserting buffers between modules to limit changes to inter-module signals during ASIC design and synthesis
KR102342001B1 (ko) 2020-05-26 2021-12-24 어보브반도체 주식회사 압축기의 제어 장치 및 압축기의 제어 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2131577B (en) * 1982-09-04 1985-10-02 Marconi Co Ltd Circuit route planning
US4612618A (en) * 1983-06-10 1986-09-16 Rca Corporation Hierarchical, computerized design of integrated circuits
GB8329888D0 (en) * 1983-11-09 1983-12-14 Philips Electronic Associated Generating component interconection lists
US4615011A (en) * 1983-12-19 1986-09-30 Ibm Iterative method for establishing connections and resulting product
JP2510058B2 (ja) * 1992-09-08 1996-06-26 新日本製鐵株式会社 スパイラル鋼管における電気抵抗溶接装置

Also Published As

Publication number Publication date
JPS6156435A (ja) 1986-03-22
JPH0527982B2 (de) 1993-04-22
EP0170501B1 (de) 1990-10-03
EP0170501A2 (de) 1986-02-05
EP0170501A3 (en) 1987-10-28
US4823278A (en) 1989-04-18
KR900000176B1 (en) 1990-01-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee