DE3682305D1 - Integrierte digitale schaltungen. - Google Patents

Integrierte digitale schaltungen.

Info

Publication number
DE3682305D1
DE3682305D1 DE8686301545T DE3682305T DE3682305D1 DE 3682305 D1 DE3682305 D1 DE 3682305D1 DE 8686301545 T DE8686301545 T DE 8686301545T DE 3682305 T DE3682305 T DE 3682305T DE 3682305 D1 DE3682305 D1 DE 3682305D1
Authority
DE
Germany
Prior art keywords
digital circuits
integrated digital
integrated
circuits
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686301545T
Other languages
English (en)
Inventor
Stuart George Hale
Finbar Naven
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB858507612A external-priority patent/GB8507612D0/en
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Application granted granted Critical
Publication of DE3682305D1 publication Critical patent/DE3682305D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
DE8686301545T 1985-03-23 1986-03-05 Integrierte digitale schaltungen. Expired - Fee Related DE3682305D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB858507612A GB8507612D0 (en) 1985-03-23 1985-03-23 Digital integrated circuits
GB858518857A GB8518857D0 (en) 1985-03-23 1985-07-25 Digital integrated circuits

Publications (1)

Publication Number Publication Date
DE3682305D1 true DE3682305D1 (de) 1991-12-12

Family

ID=26289020

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686301545T Expired - Fee Related DE3682305D1 (de) 1985-03-23 1986-03-05 Integrierte digitale schaltungen.

Country Status (5)

Country Link
US (1) US4701916A (de)
EP (1) EP0196171B1 (de)
JP (1) JP2636839B2 (de)
AU (1) AU582633B2 (de)
DE (1) DE3682305D1 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3639577A1 (de) * 1986-11-20 1988-05-26 Siemens Ag Logikbaustein zur erzeugung von ungleich verteilten zufallsmustern fuer integrierte schaltungen
FR2611052B1 (fr) * 1987-02-17 1989-05-26 Thomson Csf Dispositif de test de circuit electrique et circuit comportant ledit dispositif
US5043985A (en) * 1987-05-05 1991-08-27 Industrial Technology Research Institute Integrated circuit testing arrangement
US4831623A (en) * 1987-07-16 1989-05-16 Raytheon Company Swap scan testing of digital logic
US4847839A (en) * 1987-08-26 1989-07-11 Honeywell Inc. Digital registers with serial accessed mode control bit
US4912709A (en) * 1987-10-23 1990-03-27 Control Data Corporation Flexible VLSI on-chip maintenance and test system with unit I/O cell design
US5101498A (en) * 1987-12-31 1992-03-31 Texas Instruments Incorporated Pin selectable multi-mode processor
KR910005615B1 (ko) * 1988-07-18 1991-07-31 삼성전자 주식회사 프로그래머블 순차코오드 인식회로
US5084874A (en) * 1988-09-07 1992-01-28 Texas Instruments Incorporated Enhanced test circuit
DE68921269T2 (de) * 1988-09-07 1995-06-22 Texas Instruments Inc Integrierte Prüfschaltung.
US6304987B1 (en) 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
US4963824A (en) * 1988-11-04 1990-10-16 International Business Machines Corporation Diagnostics of a board containing a plurality of hybrid electronic components
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
US4918691A (en) * 1989-05-30 1990-04-17 Ford Aerospace Corporation Testing of integrated circuit modules
JP3005250B2 (ja) 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
JP2618723B2 (ja) * 1989-11-14 1997-06-11 三菱電機株式会社 テスト回路
DE69031865T2 (de) * 1990-02-28 1998-08-06 Texas Instruments Inc Ein SIMD-Prozessor als digitales Filter
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
US5230000A (en) * 1991-04-25 1993-07-20 At&T Bell Laboratories Built-in self-test (bist) circuit
US5515383A (en) * 1991-05-28 1996-05-07 The Boeing Company Built-in self-test system and method for self test of an integrated circuit
US5369648A (en) * 1991-11-08 1994-11-29 Ncr Corporation Built-in self-test circuit
CH685793A5 (de) * 1994-04-07 1995-09-29 Alcatel Str Ag Zufallszahlengenerator für örtlich verteilte Verbraucher.
JP3469941B2 (ja) * 1994-07-15 2003-11-25 三菱電機株式会社 プログラム実行制御装置および方法
US5699506A (en) * 1995-05-26 1997-12-16 National Semiconductor Corporation Method and apparatus for fault testing a pipelined processor
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
JPH11185497A (ja) * 1997-12-24 1999-07-09 Mitsubishi Electric Corp 半導体記憶装置
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
ATE384331T1 (de) * 2001-11-12 2008-02-15 Siemens Ag Speichertest
GB2383137B (en) 2001-12-17 2005-06-29 Micron Technology Inc DVI link with circuit and method for test
GB2383240B (en) * 2001-12-17 2005-02-16 Micron Technology Inc DVi link with parallel test data
US7376876B2 (en) * 2004-12-23 2008-05-20 Honeywell International Inc. Test program set generation tool
US11042211B2 (en) 2009-08-07 2021-06-22 Advanced Processor Architectures, Llc Serially connected computing nodes in a distributed computing system
US9429983B1 (en) 2013-09-12 2016-08-30 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US9645603B1 (en) 2013-09-12 2017-05-09 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US8022526B2 (en) 2009-08-07 2011-09-20 Advanced Processor Architectures, Llc Distributed computing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317200A (en) * 1978-10-20 1982-02-23 Vlsi Technology Research Association Method and device for testing a sequential circuit divided into a plurality of partitions
DE2902375C2 (de) * 1979-01-23 1984-05-17 Siemens AG, 1000 Berlin und 8000 München Logikbaustein für integrierte Digitalschaltungen
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
ZA834008B (en) * 1982-06-11 1984-03-28 Int Computers Ltd Data processing system
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4519078A (en) * 1982-09-29 1985-05-21 Storage Technology Corporation LSI self-test method
US4488259A (en) * 1982-10-29 1984-12-11 Ibm Corporation On chip monitor
US4513418A (en) * 1982-11-08 1985-04-23 International Business Machines Corporation Simultaneous self-testing system
US4567593A (en) * 1983-10-06 1986-01-28 Honeywell Information Systems Inc. Apparatus for verification of a signal transfer in a preselected path in a data processing system
US4534028A (en) * 1983-12-01 1985-08-06 Siemens Corporate Research & Support, Inc. Random testing using scan path technique
US4680539A (en) * 1983-12-30 1987-07-14 International Business Machines Corp. General linear shift register
US4635261A (en) * 1985-06-26 1987-01-06 Motorola, Inc. On chip test system for configurable gate arrays

Also Published As

Publication number Publication date
AU5502186A (en) 1986-09-25
EP0196171B1 (de) 1991-11-06
US4701916A (en) 1987-10-20
EP0196171A3 (en) 1989-02-01
AU582633B2 (en) 1989-04-06
JP2636839B2 (ja) 1997-07-30
EP0196171A2 (de) 1986-10-01
JPS61223675A (ja) 1986-10-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee