DE3677922D1 - Digitale phasenverriegelte schleifenschaltungen. - Google Patents

Digitale phasenverriegelte schleifenschaltungen.

Info

Publication number
DE3677922D1
DE3677922D1 DE8686117500T DE3677922T DE3677922D1 DE 3677922 D1 DE3677922 D1 DE 3677922D1 DE 8686117500 T DE8686117500 T DE 8686117500T DE 3677922 T DE3677922 T DE 3677922T DE 3677922 D1 DE3677922 D1 DE 3677922D1
Authority
DE
Germany
Prior art keywords
locked loop
digital phase
loop circuits
circuits
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686117500T
Other languages
English (en)
Inventor
Bruno Carlo Mogavero
Renato Ambrosio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecom Italia SpA
Original Assignee
CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSELT Centro Studi e Laboratori Telecomunicazioni SpA filed Critical CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Application granted granted Critical
Publication of DE3677922D1 publication Critical patent/DE3677922D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE8686117500T 1985-12-17 1986-12-16 Digitale phasenverriegelte schleifenschaltungen. Expired - Lifetime DE3677922D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT68061/85A IT1184024B (it) 1985-12-17 1985-12-17 Perfezionamenti ai circuiti ad aggancio di fase numerici

Publications (1)

Publication Number Publication Date
DE3677922D1 true DE3677922D1 (de) 1991-04-11

Family

ID=11307561

Family Applications (2)

Application Number Title Priority Date Filing Date
DE198686117500T Pending DE228021T1 (de) 1985-12-17 1986-12-16 Digitale phasenverriegelte schleifenschaltungen.
DE8686117500T Expired - Lifetime DE3677922D1 (de) 1985-12-17 1986-12-16 Digitale phasenverriegelte schleifenschaltungen.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE198686117500T Pending DE228021T1 (de) 1985-12-17 1986-12-16 Digitale phasenverriegelte schleifenschaltungen.

Country Status (6)

Country Link
US (1) US4763342A (de)
EP (1) EP0228021B1 (de)
JP (1) JPH0744449B2 (de)
CA (1) CA1280473C (de)
DE (2) DE228021T1 (de)
IT (1) IT1184024B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63214618A (ja) * 1987-03-03 1988-09-07 Yamaha Corp デジタル・フェイズ・ロックド・ル−プ
DE3719582C2 (de) * 1987-06-12 1999-01-28 Philips Broadcast Television S Schaltungsanordnung zur Erzeugung eines Phasenreferenzsignals
EP0310088B1 (de) * 1987-10-01 1996-06-05 Sharp Kabushiki Kaisha Digitale Phasenregelschleifen-Anordnung
EP0312671B1 (de) * 1987-10-19 1993-01-27 International Business Machines Corporation Prädiktive Taktwiedergewinnungsschaltung
JP2656288B2 (ja) * 1988-02-29 1997-09-24 株式会社東芝 位相検波回路
US4887071A (en) * 1988-08-18 1989-12-12 Siemens Transmission Systems, Inc. Digital activity loss detector
DE4007293A1 (de) * 1990-03-08 1991-09-12 Philips Patentverwaltung Schaltungsanordnung zum erzeugen einer vorgegebenen anzahl ausgangsimpulse
US5162910A (en) * 1990-10-03 1992-11-10 Thomson Consumer Electronics, Inc. Synchronizing circuit
US5416809A (en) * 1991-03-13 1995-05-16 Sony Corporation Digital phase locked loop apparatus
FR2682244B1 (fr) * 1991-10-04 1995-01-13 Cit Alcatel Dispositif de synchronisation pour equipement d'extremite d'un reseau de telecommunications numerique a transfert en mode asynchrone.
FR2682236B1 (fr) * 1991-10-04 1997-01-03 Cit Alcatel Procede et dispositif de commande de mode de fonctionnement d'une boucle a verrouillage de phase numerique
US5142651A (en) * 1991-10-09 1992-08-25 United States Of America As Represented By The Secretary Of The Navy Uninterrupted, enhanced-rate, event-time recorder with mixed-speed counter modules
US5612981A (en) * 1994-02-15 1997-03-18 Philips Electronics North America Corporation Apparatus and methods for improving timing recovery of a system clock
GB2379027B (en) * 2001-08-02 2004-12-22 Daidalos Inc Pulse peak and/or trough detector
US8619938B2 (en) * 2007-12-28 2013-12-31 Mediatek Inc. Clock generation devices and methods
CN112564693B (zh) * 2020-12-18 2024-01-05 北京自动化控制设备研究所 一种自适应守时授时方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142177A (en) * 1976-08-12 1979-02-27 Motorola, Inc. Digital tone decoder system
US4280099A (en) * 1979-11-09 1981-07-21 Sperry Corporation Digital timing recovery system
JPS57173230A (en) * 1981-04-17 1982-10-25 Hitachi Ltd Phase synchronizing circuit
US4466111A (en) * 1981-11-27 1984-08-14 Gte Products Corporation Synchronization apparatus and method
DE3321530A1 (de) * 1983-06-15 1984-12-20 Diehl Gmbh & Co Verfahren zur erzeugung von steuersignalen in einer vorgebbaren phasenlage, schaltungsanordnung zur durchfuehrung des verfahrens und verwendung der schaltungsanordnung
US4628519A (en) * 1984-04-06 1986-12-09 Advanced Micro Devices, Inc. Digital phase-locked loop circuit
US4626796A (en) * 1985-03-01 1986-12-02 General Electric Company Digital apparatus and method for programmably phase shifting an audio tone

Also Published As

Publication number Publication date
US4763342A (en) 1988-08-09
EP0228021A2 (de) 1987-07-08
EP0228021B1 (de) 1991-03-06
JPS62145924A (ja) 1987-06-30
EP0228021A3 (en) 1989-03-08
IT8568061A0 (it) 1985-12-17
JPH0744449B2 (ja) 1995-05-15
DE228021T1 (de) 1989-07-13
CA1280473C (en) 1991-02-19
IT1184024B (it) 1987-10-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee