DE3485112D1 - Verfahren zur bildung logischer schaltungen. - Google Patents

Verfahren zur bildung logischer schaltungen.

Info

Publication number
DE3485112D1
DE3485112D1 DE8484113322T DE3485112T DE3485112D1 DE 3485112 D1 DE3485112 D1 DE 3485112D1 DE 8484113322 T DE8484113322 T DE 8484113322T DE 3485112 T DE3485112 T DE 3485112T DE 3485112 D1 DE3485112 D1 DE 3485112D1
Authority
DE
Germany
Prior art keywords
logical circuits
forming logical
forming
circuits
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484113322T
Other languages
English (en)
Inventor
William Robert Griffin
Lawrence Griffith Heller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3485112D1 publication Critical patent/DE3485112D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8484113322T 1983-11-21 1984-11-06 Verfahren zur bildung logischer schaltungen. Expired - Fee Related DE3485112D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/554,148 US4591993A (en) 1983-11-21 1983-11-21 Methodology for making logic circuits

Publications (1)

Publication Number Publication Date
DE3485112D1 true DE3485112D1 (de) 1991-10-31

Family

ID=24212228

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484113322T Expired - Fee Related DE3485112D1 (de) 1983-11-21 1984-11-06 Verfahren zur bildung logischer schaltungen.

Country Status (4)

Country Link
US (1) US4591993A (de)
EP (1) EP0142766B1 (de)
JP (1) JPS60117757A (de)
DE (1) DE3485112D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703435A (en) * 1984-07-16 1987-10-27 International Business Machines Corporation Logic Synthesizer
US4700316A (en) * 1985-03-01 1987-10-13 International Business Machines Corporation Automated book layout in static CMOS
JPH0668756B2 (ja) * 1985-04-19 1994-08-31 株式会社日立製作所 回路自動変換方法
US4792909A (en) * 1986-04-07 1988-12-20 Xerox Corporation Boolean logic layout generator
US4745084A (en) * 1986-11-12 1988-05-17 Vlsi Technology, Inc. Method of making a customized semiconductor integrated device
US4782249A (en) * 1987-08-03 1988-11-01 General Electric Company Static CMOS programmable logic array
US4870598A (en) * 1987-08-04 1989-09-26 Texas Instruments Incorporated Comprehensive logic circuit layout system
US5150309A (en) * 1987-08-04 1992-09-22 Texas Instruments Incorporated Comprehensive logic circuit layout system
US5119313A (en) * 1987-08-04 1992-06-02 Texas Instruments Incorporated Comprehensive logic circuit layout system
US4916627A (en) * 1987-12-02 1990-04-10 International Business Machines Corporation Logic path length reduction using boolean minimization
US5173864A (en) * 1988-08-20 1992-12-22 Kabushiki Kaisha Toshiba Standard cell and standard-cell-type integrated circuit
US4928160A (en) * 1989-01-17 1990-05-22 Ncr Corporation Gate isolated base cell structure with off-grid gate polysilicon pattern
US5243538B1 (en) * 1989-08-09 1995-11-07 Hitachi Ltd Comparison and verification system for logic circuits and method thereof
US5237513A (en) * 1989-11-20 1993-08-17 Massachusetts Institute Of Technology Optimal integrated circuit generation
US5084824A (en) * 1990-03-29 1992-01-28 National Semiconductor Corporation Simulation model generation from a physical data base of a combinatorial circuit
US5313119A (en) * 1991-03-18 1994-05-17 Crosspoint Solutions, Inc. Field programmable gate array
US5524082A (en) * 1991-06-28 1996-06-04 International Business Machines Corporation Redundancy removal using quasi-algebraic methods
US5416719A (en) * 1992-12-17 1995-05-16 Vlsi Technology, Inc. Computerized generation of truth tables for sequential and combinatorial cells
JP3182036B2 (ja) * 1994-02-16 2001-07-03 松下電器産業株式会社 論理合成方法及び論理合成装置
US5629636A (en) * 1994-10-19 1997-05-13 Crosspoint Solutions, Inc. Ram-logic tile for field programmable gate arrays
US5465055A (en) * 1994-10-19 1995-11-07 Crosspoint Solutions, Inc. RAM-logic tile for field programmable gate arrays
US6240542B1 (en) * 1998-07-14 2001-05-29 Lsi Logic Corporation Poly routing for chip interconnects with minimal impact on chip performance
US7877711B2 (en) * 2006-03-01 2011-01-25 Nangate A/S Methods of deriving switch networks
US8370115B2 (en) * 2007-05-15 2013-02-05 Broadcom Corporation Systems and methods of improved boolean forms

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3252011A (en) * 1964-03-16 1966-05-17 Rca Corp Logic circuit employing transistor means whereby steady state power dissipation is minimized
US3643232A (en) * 1967-06-05 1972-02-15 Texas Instruments Inc Large-scale integration of electronic systems in microminiature form
NL176029C (nl) * 1973-02-01 1985-02-01 Philips Nv Geintegreerde logische schakeling met komplementaire transistoren.
JPS5620734B2 (de) * 1973-07-31 1981-05-15
JPS5244551A (en) * 1975-10-06 1977-04-07 Toshiba Corp Logic circuit
US4356504A (en) * 1980-03-28 1982-10-26 International Microcircuits, Inc. MOS Integrated circuit structure for discretionary interconnection
US4482810A (en) * 1982-09-30 1984-11-13 Storage Technology Partners Electron beam exposure system
JPS6010816A (ja) * 1983-06-27 1985-01-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 差動論理回路

Also Published As

Publication number Publication date
US4591993A (en) 1986-05-27
EP0142766A3 (en) 1986-07-23
JPS60117757A (ja) 1985-06-25
JPH0544853B2 (de) 1993-07-07
EP0142766A2 (de) 1985-05-29
EP0142766B1 (de) 1991-09-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee