DE3219284A1 - Verfahren zum herstellen einer halbleitervorrichtung - Google Patents

Verfahren zum herstellen einer halbleitervorrichtung

Info

Publication number
DE3219284A1
DE3219284A1 DE19823219284 DE3219284A DE3219284A1 DE 3219284 A1 DE3219284 A1 DE 3219284A1 DE 19823219284 DE19823219284 DE 19823219284 DE 3219284 A DE3219284 A DE 3219284A DE 3219284 A1 DE3219284 A1 DE 3219284A1
Authority
DE
Germany
Prior art keywords
layer
ion etching
tasi
plasma
ccl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19823219284
Other languages
German (de)
English (en)
Other versions
DE3219284C2 (https=
Inventor
Jean Serge 07974 New Providence N.J. Deslauriers
Hyman Joseph 07922 Berkeley Heights N.J. Levinstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE3219284A1 publication Critical patent/DE3219284A1/de
Application granted granted Critical
Publication of DE3219284C2 publication Critical patent/DE3219284C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition

Landscapes

  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19823219284 1981-05-22 1982-05-22 Verfahren zum herstellen einer halbleitervorrichtung Granted DE3219284A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26643381A 1981-05-22 1981-05-22

Publications (2)

Publication Number Publication Date
DE3219284A1 true DE3219284A1 (de) 1982-12-16
DE3219284C2 DE3219284C2 (https=) 1989-08-10

Family

ID=23014579

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19823219284 Granted DE3219284A1 (de) 1981-05-22 1982-05-22 Verfahren zum herstellen einer halbleitervorrichtung

Country Status (8)

Country Link
JP (1) JPS57198633A (https=)
BE (1) BE893251A (https=)
CA (1) CA1202597A (https=)
DE (1) DE3219284A1 (https=)
FR (1) FR2506519B1 (https=)
GB (1) GB2098931B (https=)
IT (1) IT1151209B (https=)
NL (1) NL8202103A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3315719A1 (de) * 1983-04-29 1984-10-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsiliziden bzw. silizid-polysilizium bestehenden doppelschichten fuer integrierte halbleiterschaltungen durch reaktives ionenaetzen
DE4114741A1 (de) * 1990-07-04 1992-01-16 Mitsubishi Electric Corp Verfahren und vorrichtung zur bildung eines verbindungsmusters und halbleitereinrichtung mit einem derartigen verbindungsmuster

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3216823A1 (de) * 1982-05-05 1983-11-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsilizid und polysilizium bestehenden doppelschichten auf integrierte halbleiterschaltungen enthaltenden substraten durch reaktives ionenaetzen
US4414057A (en) * 1982-12-03 1983-11-08 Inmos Corporation Anisotropic silicide etching process
US4528066A (en) * 1984-07-06 1985-07-09 Ibm Corporation Selective anisotropic reactive ion etching process for polysilicide composite structures
NL8500771A (nl) * 1985-03-18 1986-10-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een op een laag siliciumoxide aanwezige dubbellaag - bestaande uit poly-si en een silicide - in een plasma wordt geetst.
EP0229104A1 (en) * 1985-06-28 1987-07-22 AT&T Corp. Procedure for fabricating devices involving dry etching
US6177337B1 (en) * 1998-01-06 2001-01-23 International Business Machines Corporation Method of reducing metal voids in semiconductor device interconnection

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519873A (en) * 1978-07-28 1980-02-12 Mitsubishi Electric Corp Forming method of metallic layer pattern for semiconductor

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
"IBM Techn. Discl. Bull.", Bd. 19, Nr. 9, Februar 1977, S. 3366 *
"IEEE Journal of Solid-State Circuits", Bd. SC-15, Nr. 4, August 1980, S. 411-416 *
"IEEE Transactions on Electron Devices", Bd. ED-26, Nr. 4, April 1979,S. 369-371 *
"J. Vac. Sci. Technol.", Bd. 17, Nr. 4, Juli/August 1980, S. 775-792 *
"Philips techn. Rdsch.", Bd. 38, Nr. 7/8, 1979, S. 203-214 *
"Solid State Technology", November 1980, H.11, S. 85-91 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3315719A1 (de) * 1983-04-29 1984-10-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsiliziden bzw. silizid-polysilizium bestehenden doppelschichten fuer integrierte halbleiterschaltungen durch reaktives ionenaetzen
DE4114741A1 (de) * 1990-07-04 1992-01-16 Mitsubishi Electric Corp Verfahren und vorrichtung zur bildung eines verbindungsmusters und halbleitereinrichtung mit einem derartigen verbindungsmuster
DE4114741C2 (de) * 1990-07-04 1998-11-12 Mitsubishi Electric Corp Verfahren zur Bildung einer Leiterbahn auf einem Halbleitersubstrat

Also Published As

Publication number Publication date
IT1151209B (it) 1986-12-17
DE3219284C2 (https=) 1989-08-10
GB2098931A (en) 1982-12-01
FR2506519A1 (fr) 1982-11-26
FR2506519B1 (fr) 1985-07-26
BE893251A (fr) 1982-09-16
JPS57198633A (en) 1982-12-06
IT8221430A0 (it) 1982-05-21
NL8202103A (nl) 1982-12-16
GB2098931B (en) 1985-02-06
CA1202597A (en) 1986-04-01

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8127 New person/name/address of the applicant

Owner name: AT & T TECHNOLOGIES, INC., NEW YORK, N.Y., US

D2 Grant after examination
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee