DE69130787T2 - Ätzverfahren für eine leitende Doppelschicht-Struktur - Google Patents

Ätzverfahren für eine leitende Doppelschicht-Struktur

Info

Publication number
DE69130787T2
DE69130787T2 DE69130787T DE69130787T DE69130787T2 DE 69130787 T2 DE69130787 T2 DE 69130787T2 DE 69130787 T DE69130787 T DE 69130787T DE 69130787 T DE69130787 T DE 69130787T DE 69130787 T2 DE69130787 T2 DE 69130787T2
Authority
DE
Germany
Prior art keywords
layer structure
etching process
double layer
conductive double
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130787T
Other languages
English (en)
Other versions
DE69130787D1 (de
Inventor
Katsuhiko Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69130787D1 publication Critical patent/DE69130787D1/de
Application granted granted Critical
Publication of DE69130787T2 publication Critical patent/DE69130787T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69130787T 1990-08-23 1991-08-16 Ätzverfahren für eine leitende Doppelschicht-Struktur Expired - Fee Related DE69130787T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2224030A JPH0779102B2 (ja) 1990-08-23 1990-08-23 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69130787D1 DE69130787D1 (de) 1999-03-04
DE69130787T2 true DE69130787T2 (de) 1999-05-27

Family

ID=16807494

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130787T Expired - Fee Related DE69130787T2 (de) 1990-08-23 1991-08-16 Ätzverfahren für eine leitende Doppelschicht-Struktur

Country Status (5)

Country Link
US (1) US5487811A (de)
EP (1) EP0473344B1 (de)
JP (1) JPH0779102B2 (de)
KR (1) KR960002070B1 (de)
DE (1) DE69130787T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2871460B2 (ja) 1994-05-20 1999-03-17 株式会社日立製作所 シリコンのエッチング方法
US5910021A (en) * 1994-07-04 1999-06-08 Yamaha Corporation Manufacture of semiconductor device with fine pattens
US5652170A (en) 1996-01-22 1997-07-29 Micron Technology, Inc. Method for etching sloped contact openings in polysilicon
US5880033A (en) * 1996-06-17 1999-03-09 Applied Materials, Inc. Method for etching metal silicide with high selectivity to polysilicon
JPH1168095A (ja) * 1997-08-11 1999-03-09 Fujitsu Ltd 半導体装置の製造方法
US6159794A (en) * 1998-05-12 2000-12-12 Advanced Micro Devices, Inc. Methods for removing silicide residue in a semiconductor device
US20060237398A1 (en) * 2002-05-08 2006-10-26 Dougherty Mike L Sr Plasma-assisted processing in a manufacturing line
US20060228497A1 (en) * 2002-05-08 2006-10-12 Satyendra Kumar Plasma-assisted coating
US20060233682A1 (en) * 2002-05-08 2006-10-19 Cherian Kuruvilla A Plasma-assisted engine exhaust treatment
US6870124B2 (en) * 2002-05-08 2005-03-22 Dana Corporation Plasma-assisted joining
US7432470B2 (en) 2002-05-08 2008-10-07 Btu International, Inc. Surface cleaning and sterilization
US8349241B2 (en) * 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
US7189940B2 (en) * 2002-12-04 2007-03-13 Btu International Inc. Plasma-assisted melting
KR100497474B1 (ko) * 2003-06-20 2005-07-01 주식회사 하이닉스반도체 반도체소자의 게이트전극 형성방법
WO2006127037A2 (en) * 2004-11-05 2006-11-30 Dana Corporation Atmospheric pressure processing using microwave-generated plasmas
US7544621B2 (en) * 2005-11-01 2009-06-09 United Microelectronics Corp. Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method
JP2006303496A (ja) * 2006-04-14 2006-11-02 Fujitsu Ltd 半導体装置の製造方法
JP5264383B2 (ja) * 2008-09-17 2013-08-14 東京エレクトロン株式会社 ドライエッチング方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539742A (en) * 1981-06-22 1985-09-10 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
JPS59162276A (ja) * 1983-03-07 1984-09-13 Toshiba Corp 反応性イオンエツチング方法
NL8500771A (nl) * 1985-03-18 1986-10-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een op een laag siliciumoxide aanwezige dubbellaag - bestaande uit poly-si en een silicide - in een plasma wordt geetst.
US4784720A (en) * 1985-05-03 1988-11-15 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
JPS62111432A (ja) * 1985-11-08 1987-05-22 Fujitsu Ltd 半導体装置の製造方法
US4789426A (en) * 1987-01-06 1988-12-06 Harris Corp. Process for performing variable selectivity polysilicon etch
US4778563A (en) * 1987-03-26 1988-10-18 Applied Materials, Inc. Materials and methods for etching tungsten polycides using silicide as a mask
US4799991A (en) * 1987-11-02 1989-01-24 Motorola, Inc. Process for preferentially etching polycrystalline silicon
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
EP0328350B1 (de) * 1988-02-09 1999-04-28 Fujitsu Limited Trockenätzen mit Wasserstoffbromid oder Brom
US5007982A (en) * 1988-07-11 1991-04-16 North American Philips Corporation Reactive ion etching of silicon with hydrogen bromide
JPH0294520A (ja) * 1988-09-30 1990-04-05 Toshiba Corp ドライエッチング方法
US5030590A (en) * 1989-06-09 1991-07-09 Applied Materials, Inc. Process for etching polysilicon layer in formation of integrated circuit structure
US5110411A (en) * 1990-04-27 1992-05-05 Micron Technology, Inc. Method of isotropically dry etching a poly/WSix sandwich structure

Also Published As

Publication number Publication date
DE69130787D1 (de) 1999-03-04
KR960002070B1 (ko) 1996-02-10
US5487811A (en) 1996-01-30
EP0473344A3 (en) 1992-03-25
EP0473344A2 (de) 1992-03-04
JPH04105321A (ja) 1992-04-07
EP0473344B1 (de) 1999-01-20
JPH0779102B2 (ja) 1995-08-23
KR920005271A (ko) 1992-03-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee