DE68929268T2 - Herstellungsprozess für bipolare Sinkerstruktur - Google Patents

Herstellungsprozess für bipolare Sinkerstruktur

Info

Publication number
DE68929268T2
DE68929268T2 DE68929268T DE68929268T DE68929268T2 DE 68929268 T2 DE68929268 T2 DE 68929268T2 DE 68929268 T DE68929268 T DE 68929268T DE 68929268 T DE68929268 T DE 68929268T DE 68929268 T2 DE68929268 T2 DE 68929268T2
Authority
DE
Germany
Prior art keywords
bipolar
manufacturing process
sinker structure
sinker
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68929268T
Other languages
English (en)
Other versions
DE68929268D1 (de
Inventor
Larry Joseph Pollock
Atiye Bayman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Synergy Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synergy Semiconductor Corp filed Critical Synergy Semiconductor Corp
Application granted granted Critical
Publication of DE68929268D1 publication Critical patent/DE68929268D1/de
Publication of DE68929268T2 publication Critical patent/DE68929268T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
DE68929268T 1988-12-28 1989-12-28 Herstellungsprozess für bipolare Sinkerstruktur Expired - Fee Related DE68929268T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/291,185 US5001538A (en) 1988-12-28 1988-12-28 Bipolar sinker structure and process for forming same

Publications (2)

Publication Number Publication Date
DE68929268D1 DE68929268D1 (de) 2001-01-04
DE68929268T2 true DE68929268T2 (de) 2001-04-12

Family

ID=23119247

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68929268T Expired - Fee Related DE68929268T2 (de) 1988-12-28 1989-12-28 Herstellungsprozess für bipolare Sinkerstruktur

Country Status (4)

Country Link
US (1) US5001538A (de)
EP (1) EP0376722B1 (de)
JP (1) JPH02263442A (de)
DE (1) DE68929268T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614750A (en) * 1995-06-29 1997-03-25 Northern Telecom Limited Buried layer contact for an integrated circuit structure
US6703679B1 (en) 1999-08-31 2004-03-09 Analog Devices, Imi, Inc. Low-resistivity microelectromechanical structures with co-fabricated integrated circuit
US6818958B2 (en) * 2001-04-13 2004-11-16 International Rectifier Corporation Semiconductor device and process for its manufacture to increase threshold voltage stability
US6699765B1 (en) * 2002-08-29 2004-03-02 Micrel, Inc. Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer
EP1696485A1 (de) 2005-02-24 2006-08-30 STMicroelectronics S.r.l. Verfahren zur Herstellung von Halbleiterbauelementen in einem SOI-Substrat mit Justiermarken

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4047220A (en) * 1975-12-24 1977-09-06 General Electric Company Bipolar transistor structure having low saturation resistance
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4691219A (en) * 1980-07-08 1987-09-01 International Business Machines Corporation Self-aligned polysilicon base contact structure
EP0068070A1 (de) * 1981-07-01 1983-01-05 Rockwell International Corporation Komplementare NPN- und PNP-Lateraltransistoren, die zur minimalen Beeinflussung durch mit Substratoxyd gefüllte Rillen vom Substrat getrennt sind, und Verfahren zu ihrer Herstellung
JPS5992548A (ja) * 1982-11-18 1984-05-28 Toshiba Corp 半導体装置及びその製造方法
US4738936A (en) * 1983-07-01 1988-04-19 Acrian, Inc. Method of fabrication lateral FET structure having a substrate to source contact
US4595944A (en) * 1983-12-29 1986-06-17 International Business Machines Corporation Resistor structure for transistor having polysilicon base contacts
JPS61164262A (ja) * 1985-01-17 1986-07-24 Toshiba Corp 半導体装置
US4674173A (en) * 1985-06-28 1987-06-23 Texas Instruments Incorporated Method for fabricating bipolar transistor
US4808548A (en) * 1985-09-18 1989-02-28 Advanced Micro Devices, Inc. Method of making bipolar and MOS devices on same integrated circuit substrate
US4721682A (en) * 1985-09-25 1988-01-26 Monolithic Memories, Inc. Isolation and substrate connection for a bipolar integrated circuit
US4686763A (en) * 1985-10-02 1987-08-18 Advanced Micro Devices, Inc. Method of making a planar polysilicon bipolar device
EP0255973A2 (de) * 1986-08-08 1988-02-17 SILICONIX Incorporated Kontakte von Halbleiterbauelementen gebildet auf einem minimalen Gebiet der Oberfläche
US4868921A (en) * 1986-09-05 1989-09-19 General Electric Company High voltage integrated circuit devices electrically isolated from an integrated circuit substrate
GB8621534D0 (en) * 1986-09-08 1986-10-15 British Telecomm Bipolar fabrication process
US4745087A (en) * 1987-01-13 1988-05-17 Advanced Micro Devices, Inc. Method of making fully self-aligned bipolar transistor involving a polysilicon collector contact formed in a slot with an oxide sidewall
US4847670A (en) * 1987-05-11 1989-07-11 International Business Machines Corporation High performance sidewall emitter transistor
EP0316562A3 (de) * 1987-11-19 1989-08-09 Texas Instruments Incorporated Halbleiterbipolartransistor mit Basis und Emitterstruktur in einem Graben und Verfahren zu seiner Herstellung
US4839305A (en) * 1988-06-28 1989-06-13 Texas Instruments Incorporated Method of making single polysilicon self-aligned transistor

Also Published As

Publication number Publication date
EP0376722A2 (de) 1990-07-04
US5001538A (en) 1991-03-19
JPH02263442A (ja) 1990-10-26
EP0376722B1 (de) 2000-11-29
EP0376722A3 (de) 1990-10-17
DE68929268D1 (de) 2001-01-04

Similar Documents

Publication Publication Date Title
DE69029193D1 (de) Steuerungssystem für herstellungsverfahren
DE68927860D1 (de) Borkarbidherstellung
DE68915443D1 (de) Herstellungsmethode linearen faseranordnung.
ES536023A0 (es) Tricotosa rectilinea
DE68920824D1 (de) Herstellungsverfahren für Polyimidfasern.
DE69117905D1 (de) Herstellungsverfahren für Alkoxyphthalocyanine
KR890701803A (ko) 초전도체의 제조법
KR890701228A (ko) 9Ok초전도체 제조를 위한 개선된 방법
DE68909868D1 (de) Koagulationsverfahren für Filamente.
DE68925327D1 (de) Strickverfahren
DE3751789D1 (de) Rundstrickmaschine
ES546833A0 (es) Maquina tricotosa
DE68928905D1 (de) Muster-Herstellungsverfahren
DE68929268D1 (de) Herstellungsprozess für bipolare Sinkerstruktur
KR880021907U (ko) 편물기용 부품
IT1219932B (it) Macchina di maglieria circolare con alimetazioni multiple
ATA134988A (de) Spuelkippe
KR880021902U (ko) 뜨개 바늘
KR850009591U (ko) 편기장치
IT1183212B (it) Macchina da maglieria circolare
KR880019734U (ko) 편망기용 샤틀
KR880015061U (ko) 뜨게바늘
ATA70687A (de) Strickgeraet
KR840007323U (ko) 뜨게바늘
KR840006166U (ko) 편물 바늘

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee