CA1202597A - Reactive ion layers containing tantalum and silicon - Google Patents

Reactive ion layers containing tantalum and silicon

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Publication number
CA1202597A
CA1202597A CA000401014A CA401014A CA1202597A CA 1202597 A CA1202597 A CA 1202597A CA 000401014 A CA000401014 A CA 000401014A CA 401014 A CA401014 A CA 401014A CA 1202597 A CA1202597 A CA 1202597A
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CA
Canada
Prior art keywords
tantalum
layer
polysilicon
silicon
method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000401014A
Other languages
French (fr)
Inventor
Jean S. Deslauriers
Hyman J. Levinstein
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Western Electric Co Inc
Original Assignee
Western Electric Co Inc
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Filing date
Publication date
Priority to US26643381A priority Critical
Priority to US266,433 priority
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Application granted granted Critical
Publication of CA1202597A publication Critical patent/CA1202597A/en
Application status is Expired legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metallic silicode formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction

Abstract

Abstract:

An advantageous low-resistivity gate level metallization for VLSI MOS devices comprises TaSi2 on polysilicon. A two-layer tantalum-silicon composite initially overlies a relatively thin gate oxide film. In accordance with this invention, the two-layer composite is anisotropically patterned in a two-step reactive ion etch-ing process. Patterning is carried out before the layers are sintered to form TaSi2. In the preferred embodiment, CC13F is utilized to etch the composite layer and some of the underlying polysilicon layer. Thereafter, utilizing C12, the remaining polysilicon is etched in a step characterized by high selectivity with respect to the underlying gate oxide film.

Description

~63 2~S~

ReaG~ive ion etchin~ of layers containin~ tantalum and silicon This invention relates a method of abricating a semiconduc~or device comprising the s~ep of plasma etching a layer through forma~ion of a plasma in an e~chant gas.
It is known to utilize a refractory metal silicide on polysilicon to achieve 2 hi~h-conductivity gate-level metallization for MOS devices. One example of such a method is disclosed in the article by S.P. Murarka, 3.B.
Fraser, A.K. Sinha and H.J. Levinstein entitled "Refractory Silicides of Titanium and Tan~alum for Low-Resistivity ln Gates and Interconnects," IEEE Journal of Solîd-State Circuits, Vol. SC-15 7 No. 4, August 1980, pages 474-482.
A tantalum-silicon on-polysilicon structure is a particularly attractive composite for use in very-large-scale-integrated ~VLSI) MOS devices to form, for example, high-resolution gate elec~rodes. ~he effective utiliza~ion of such a composite requires that fabrication techniques be available for patterning the tantalum-silicon and poly-silicon layers anisotropically with minimal linewidth loss.
Accordingl~, efforts have been directed at trying to devise high-resolution etching processes for patterning such layers. Heretofore, however, known efforts to devise an effective etching process for tantalum-silicon-on-~

.:

$2~

polysilicon adequate for defining high-resolution features in VLSI device~ have not been successfulO
These problems are solved in accordance with the invention in a process for plasma etching a layer charac-terized in that the layer contains tantalum and silicon compcnents, and the etchant includes fluorine and chlorine components as the predominant etchant species for ~he tantalum and silicon components, respectively.
In accordance with an aspect of the invention there is provided a method of fabricating a patterned tantalum disilicide structure on a subs~rate, comprising providing tantalum and silicon on the substrate~ first forming a patterned structure comprising said ma~erials by plasma etching tantalum and silicon using an etchant which includes fluorine and chlorine as the predominant etchant species for tantalum and silicon, respectively~ and there-after sintering said structure to convert said materials to tantalum disilicide.
In the drawing:
Figure 1 is a schematic representation of a conventional reactive ion etching apparatus of the type in which applicant's process is carried out; and Figures 2 through 4 are idealized showinys, not to scale, of a portion of a specific illustrative workpiece that is patterned in accordance with the principles of the present invention.
An object of an illustrative embodiment of the present invention is an improved process for making VLSI
devices, More specifically, an object is a dry etching process for high-resolution patterning of tantalum-silicon-on-polysilicon composite structures for VLSI MOS devices.
Briefly, these and other objects of the present invention are realized in a specific illustrative embodi-ment thereof in which tantalum-silicon and polysilicon layers overlying a gate oxide film are anisotropically pat-terned in a reactive ion etching process. The tantalum-silicon comprises a layer of co~deposited tantalum and

2~

3 --silicon formed on top of the polysilicon layer.
Advantageously, in accordance with an illust~a~ive feature of the invention, etching of the indicated layers is carried out in a two-step sequence before the layers are sintered.
A masking pattern is initially formed on the tantalum-silicon layer. The tantalum-silicon layer is then etched in a reactive ion etching chamber in a plasma that comprises radicals that include fluorine and chlorine as the predominant active etching species for tantalum and silicon~ respectively. In a preferred embodiment, ~he gas introduced into the chamber to form the etching plasma comprises CC13F.
Illustratively, the tantalum-silicon layer and some lS but less than all of the underlying polysilicon layer are anisotropically etched in the aforespecified plasma.
Subsequently, the remaining polysilicon layer underlying the patterned tantalum-silicon is anisotropically etched in a plasma that etches selectively with respect to the underlying gate oxide film. By way of example, this second-mentioned plasma comprises chlorine as the predom-inant active etching species. After being patterned t the tantalum-silicon and polysilicon layers are sintered, thereby to provide a low-resistivity gate-level composite structure.
Applicants' inventive process may be carried out ;n a standard parallel-plate reactive ion etching apparatus of the type shown in Figure 1. The particular illustrative parallel-plate reactor shown in Figure 1 comprises an etching chamber 10 defined by a cylindrical nonconductive member 12 and two conductive end plates 14 and 16.
Illustratively, the member 12 is made of glass and the plates 14 and 16 are made of aluminum and stainless steel, respectively. In addition, the depicted reactor includes a conductive workpiece holder 18 also made, for example, ~2~25~

of aluminum. In one illustrative case, the top of the holder 18 constitutes a 10-inch circular surface designed to have seven 3-inch wafers placed ~hereon. Three such wafers 20 through 22 are shown in Figure 1.
S The workpiece holder 18 (Figure 1) is capacitively coupled via a standard matching network 26 to a radio-frequency generator 28 which, by way of example, is designed ~o drive the holder 18 al: a frequency of 13.56 megahertz.
In Figure 1, the top plate 14 is connected to a point of reference potential such as ground. The plate 14 is the anode of the depicted reactor. The workpiece holder 18 constitute~ the driven cathode of the reactor. In one specific illustrative reactor of the type shown in Figure 1~ the anode-to-cathode separation was approximately 6 inches and the diameter of the anode plate 14 was approxi-mately 18 inches.
The base plate 16 of the Figure 1 arrangement is also connected to ground. Additionally, an open-ended cylind-rical shield 30 surrounding the holder 18 is connected to the plate 16 and thus to ground. The portion of the holder 18 that extends through the plate 16 is electrically insulated therefrom by a nonconductive bushing 32.
In accordance with the principles of the present invention, particular gaseous atmospheres, specified below, are established in the chamber 10 of Figure 1. Gas is controlled to flow into the chamber from a standard supply 34. Additionallyy a prescribed low pressure condition is maintained in the chamber 10 by means of a conventional pump system 36.
By introducing a suitable gas into the chamber 10 o~
Figure 1 from the supply 34 and establishing an electrical field between the anode 14 and the cathode 18, as specified in particular detail below, a reactive plasma is generated in the chamber 10. The plasma established therein is .

~ ~ ~ 26~ ~

characterized by a uniform dark space in the immedia~e vi~inity of the surfaces of the wafers to be etched.
Volatile products formed at the wafer sur~aces during the etchin~ process are exhausted from the chamber by the system 36.
A portion of one of the wafers 20 through 22 to be etched is shown in cross-section in Figure ~. The depicted portion includes a gate oxide film 40 formed on ~e surface vf a silicon member 42 . The f ilm 40 is grown on the member 42 to a thickness of, for example, approximately 1000 Angstrom units. On top o~ the film 40 is a 3500 Angstrom-unit-thick layer 44 of doped polysilicon. By way of example, the layer 44 is formed by low-press~re chemical vapor deposition followed by phosphorus diffusion. Further, a 2590 Angstrom-unit-thick layer 46 of tantalum-silicon is ormed on the polysilicon layer 44. Illustratively, the tantalum-silicon is deposited by co-sputtering tantalum and silicon onto the top of the layer 44, in a manner well known in the art~ At that point, before sintering, the layer 46 comprises a co-sputter-deposited metastable solid solution.
In accordance with the principles of the present invention, the layers 44 and 46 of Figure 2 are delineated in a reactive ion etching process to form a gate-level metallization pattern in an MOS device~ For this purpose, a patterned masking layer is initially formed on top of the tantal~m-silicon layer 46. The masking layer may comprise a pattern defined by, for example, standard photolitho-graphic techniques in a 10,000 Angstrom-unit-thick layer of a conventional photoresist such as HPR-204 which is a commercially available positive photoresist made by Philip A. ~unt Chemical Corp., Palisades Park, New Jersey.
It is particularly advantageous, however, to form a masking pattern for the layers 44 and 46 of Figure 2 by employing the process described by 3.M~ Moran and D. Maydan ~` ~

~Z.~g7 in 'IHigh ~e~olution, Steep ~rofile, Resist Patterns," in The Bell SYs~em Technical Journal, Volume 5~, No. 5, May-June 1979, pages 1027-1036 n This process is also described in U.S. Patent 4,244,799. ~he described process, S which is sometimes referred to as the trilevel process, is characterized by submicron resolution with excellent line-width control and step coverage.
Figure 2 depicts a highresoluti3n steep-profile mask-ing pattern made in accordance with the aforespecified trilevel processing sequence. The depicted masking pattern is shown formed in a relatively thick layer 48 made of a hardened organic material~ By way of example, the patterned layer 48 is approximately 2.5 micrometers thick and comprises HPR-206 resist baked at about 210 degrees Celsius for approximatel~y 2 hours. Deposited on top of the layer 48 is a so-called intermediate masking layer 50 approximately 1200 Angstrom-units-thick and made, for example, of plasma-deposited sllicon dioxide. In prior steps of the standard trilevel process, the layer 50 was selectively etched (in, for example, a reactive ion etching step employing a CHF3 plasma) using a thin overlying high-resolution resist pattern ~not shown) as the mask therefore. Illustratively, the hi~h-resolution resist pattern is defined by standard X-ray lithographic techniques in a layer made of a mixture of poly(2,3-dichloro-l-proply acrylate) and poly(glycidyl methacrylate-co-ethyl acrylate) also known as DCOPA resist. ~he pattern in the relatively thin layer 50 was then transferred into the underlying layer 46 to form a corresponding pattern.
This last-mentioned transfer was done, for example, in a reactive ion etching step in an 2 plasma, in a manner known in the art.
In accordance with the principles of the present invention, the masked tantalum-silicon layer 46 shown in Figure 2 is patterned in a reactive ion etching step. In , a preferred embodiment, thi~ i~ carried out in a plasma formed by introducing CC13F gas in~o the reaction chamber O . CC13~ is a commercially available gas, known as Freon`ll* or Halocarbon ll*o An etch rate of approxi-mately 2000 Angstrom units per minute and an anisotropic profile in the tantalum-silicon layer 46 were obtained under the following preferred opera~ing conditions in the etching equipment: a CC13F input flow rate of about 25 cubic centimeters per minutey a CC13F par~ial pressure of approxima~ely 5 micrometers (milliTorrs) and a power density at the surface of the wafers being etched of about 0.2 watt~ per square centimeter.
More generally, satis~actory anisotropic patterning of the tantalum-silicon layer 46 o Figure 2, ut;lizing CC13F in a reactive ion e~ching step, was achieved under the following operating conditions: a CC13F flow rate of S to 70 cubic centimeters per minute, a CC13F partial pressure of 2 to 50 microme~ers and a power densi~y of 0.04 to 006 watts per square centimeter.
Moreover, applicants have de~ermined that anisotropic reactive ion etching of tantalum-~ilicon is also achievable by utilizing CC12T2 (Freon 12*) or CC13F (Freon 13*) under the opera~ing conditions specified in the paragraph immediately above.
Further~ a generalized contemplated explanation for the aforespecified etching of tantalum silicon has been formulated by applicants. In accordance therewith, reactive ion etching of unsintered tantalum-silicon in a plasma is deemed to be primarily attributable to radicals that include fluorine and chlorine as ~he predominant active etching species for tantalu~ and silicon, respectively. The aforespecified gases are illustrative ways of supplying such radicals.

*Trade mark The etching process for tan~alum-silicon set forth above is also effective to aniso~ropically etch the polysilicon layer 44 shown in Figure 2. Accordingly, in principle~ the tantalum-silicon and polysilicon layers overlying the thin silicon dioxide layer 40 could be both entirely patterned utilizing the above~speciied plasmas.
But the etch rate therein for ~antalum-silicon and poly-silicon relative to SiO~ is only about 6 to-1~ And, since in practice some overetching of ~he tantalum-silicon-on-polysilicon structure is typically required to clear patterns over stepped surfaces or to compensate for the effects of non-uniform etching across a wafer, a better etch selectivity relative to SiO2 is usually prescribed.
To improve the aforementioned selectivity, thereby to better protect the thin gate oxide layer 40 (Figure 1) against erosion, it is advantageous to etch the wafers considered herein in a two-step reactive ion etching process. In the first step, the tantalum-silicon layer 46 and some part, for example up to approximately one-half, of the underlying polysili~on layer 44 are etched in accordance with the specific process set forth above.
At that point, the structure being fabricated appears as indicated in Figure 3.
Subsequently, to complete the etching of the partially patterned polysilicon layer 44 (Figure 3), the second step of the two-step reactive ion etching process is carried out~ Illustratively, this is done by generating a plasma that comprises radicals that include only chlorine as the predominant active etching species for the depicted structure. Such a plasma is established, or example, by introducing substantially pure C12 gas into the reactive ion etching chamber. An etch rate of approximately 1000 Angstrom units per minute and an anisotopric profile in the polysilicon layer 44 were obtained under the following preferred ~onditions in the etching equipment: a C12 - g input flow rate of about 15 cubic centimeters per minute, a C12 partial pressure of approximately 7 micrometers and a power density of about 0.2 watts per square centi-meter. Under these conditions, the polysilicon-to-SiO2 differential etch rate is approximatey 22-to-1.
Moreover~ under these conditions, the previously defined tantalum-silicon pattern also etches very 510wly (at a rate of only about 30 Angstrom units per minute). Hence, tantalum-silicon serves as an excellent mask for etching the remaining polysilicon.
More generally, satisfactory anisotropic patterning of the polysilicon layer 44 of Figure 3, utilizing C12 in a reactive ion etching step, was achieved under the following operating conditions: a C12 flow rate of 5 to 60 cubic centimeters per minute, a C12 partial pressure of 2 to 30 micrometers and a power density of 0.06 to 0~ watts per square centimeter.
At the completion of the aforespecified polysilicon etching step, the patterned structure appears as shown in Figure 4. The resist layer 48 is then removed in a standard way by, for example, chemical dissolution in a mixture f ~22 and H2SO4- Thereafter~ the remaining tantalum-silicon-on-polysilicon composite gate-level structure is sintered at, for example, about 900 ~5 degrees Celsius in pure argon for approximately 30 minutes.
After sintering, the resistivity of one such specific illustrative composite structure was measured to be approximately 2.2 ohms per square.
Finally, it i~ to be understood that the above-described techniques are only illustrative of theprinciples of the present invention. In accordance with these principles, numerous modifications and alternatives may be devised by those skilled in the art without departing from the spirit and scope of the invention.

~2~Z1,S~7 SUPPLEMENTARY 1:) I SCLOSURE

Previous attempts to produce useful tantalum silicide-on-polysilicon gates for VLSI MOS devices by reactive ion etching layers of tantalum silicide and polysilicon have failed because conductive etch residues are formed and remain wi~hin etch pits produced during the reactive ion etching of the tan~alum silicide. Thus, during the operation of ~he resulting MOS devices, the conductive etch residues can produce a short circuiting of the tantalum silicide-on-polysilicon gates.
The invention also resides in the discovery that an anisotropically patterned layer of tantalum silicide is produced, with essentially no production of conductive etch residues, by depositing tantalum and silicon onto a substrate, anisotropically patterning the tantalum and silicon by means of a reactive ion etching process, and then sintering the patterned tan~alum and silicon. The sintering reacts the tantalum and silicon to form tantaLum silicide. Thus, the invention yields an anisotropically patterned layer of tantalum silicide, and avoids the need for directly anisotropically etching tantalum silicide.
Consequently, the invention is useful for fabricating devices having high resolution tantalum silicide st~uctures, i.e., tantalum silicide structure whose widths are 2~m or smaller, which devices are essentially free of conductive etch residues.
The inventive procedure described above is, of course a~so useful for abricating devices having low resolution tan~alum silicide structures, i~e., tantalum silicide structures whose widths are greater than 2~m. Moreover, the invention also encompasses an alternative procedure for fabricating such low resolution devices. In this alternative procedure tantalum and silicon are also deposited onto a substrate, but then the tantalum and silicon are generally isotropically patterned (the maximum horizontal undercutting is greater than about one-fourth the vertical etch depth) b~; for example, conventional plasma etching techniques. ~hereafter, the tantalum and silicon is sintered. This alternative procedure is also useful or fabricating devices which are essentially free of conductive etch re.sidues.
In a specific illustrative embodiment o~ the invention, an anisotropically patterned, composite layer of tantalum silicide-on-polysilicon overlying a gate oxide film is produced by depositing a layer of polysilicon onto the gate oxide film, and then co-depositing tantalwm and silicon/ in the form of an amorphous mixture, onto the layer of polysilicon. Advantageously, in accordance with an illustrative feature o the inventon~ etching of the indicated layers is carried out in a two-step sequence before the layers are sintered.
In accordance with an aspect of the invention there is provided a method of forming a patterned layer of tantalum disilicide on a substrate comprising providing the materials tantalum and silico~ on the substrate, patterning at least said tantalum, and then reacting said ~antalum with said silicon to form said patterned tantalum disilicide layer.
In drawings which 3.11ustrate embodiment of the invention o~ the supplemen~ary disclosure:
FIGS. 5-8 depict the steps involved in a second embodiment of the inventive fabrication process; and FIGS. 9-10 depict the steps involved in a third embodiment of the inventive fabrication process.
The invention encompasses devices which include a tantalum silicide structure, and which devices are essentially free of ~onductive etch residues. The invention also encompasses a method for fabricating such devices, which method includes a series of steps for producing a patterned layer of tantalum silicide. The inventive method is useful, for example, for Eabricating VLSI MOS devices having high resolution tantalum silicide-on-polysilicon gate electrodes.

~;~Ps D~

In accordance with the inventive fabrication method, a device i5 formed by a series of steps which include the steps of depositing tantalum and silicon onto a substrate r patterning the tantalum and silicon, and then sintering the patterned tantalum and silicon. The sintering reacts the tantalum and silicon to form tantalum silicide. Thus~ a patterned tantalum silicide layer is produced without the need for directly patterning tantalum silicide. Because tantalum silicide is not directly patterned, the formation of oonductive etch residues is avoided. Consequently, deviGes formed in accordance with the invention are essentially free of conductive etch residues~
In a second embodiment of the inventive fabrication method, successive layers of polysilicon and tantalum are deposited onto a substrate, the two deposited layers are patterned, and the patterned layers are then sintered. The sintering reacts the patterned tantalu~ and polysilicon layers to form a patterned tantalum silicide layer.
In a third embodiment of the inventive fabrication method, similar to the second embodiment, only the tantalum layer (or the tantalum layer and a portion of the under-lying polysilicon layer) is patterned, and then the patterned tantalum layer and the underlying polysilicon layer are sintered. The sintering yields a patterned tantalum silicide layer overlying an unpatterned poly-sîlicon layer. The polysilicon layer is then patterned using the patterned tantalum silicide layer as an etch mask.
If devices (encompassed by the invention~ having high resolution tantalum silicide structures are to be fabricated, then the layer of co-deposited tantalum and silicon, or the success;ve layers of tantalum and poly-silicon, referred to above, are anisotropically patterned using an inventive reactive ion etching process. Of course, the anisotropic reactive ion etching process, in combination with the other inventive fabrication steps, is 5~

also useul for abricating devices (encompassed by the invention) having low resolution tantalum silicide structures. Alternatively, when fabricating devices having low resolution ~antalum silicide structures, the layer of co-deposi~ed tantalum and silicon, or the successive layers of tantalum and polysilicon, are generally isotropically patterned by means of conventional plasma etching processes.
Either fabrication procedure yields devices which are essentially free of conductive etch residues.
In accordance with the second emb~diment of the inventive fabrication method, a device having a composite tan~alum silicide-on-poLysilicon structure is fabricated by forming a wafer~ shown in cross-section in FIG. S, which, as before, includes a silicon substrate 42, a silicon dioxide film 40, and a deposited polysilicon layer 44~
However, the second embodiment of the inventive fabri~ation method differs ~rom the firs~ embodiment in that the wafer of FIG. 5 includes a deposited tantalum layer 52 ~and not an amorphous mixture of tantalum and silicon) overlying the polysilicon ~ayer 44. The tantalum layer 52 is deposited onto the polysilicon layer 44 by, for example, conventional sputtering techniques.
In forming a device, the thickness of the silicon dioxide film 40 of the wafer shown in FIG. 5 typically ranges, as before, rom about 50 to about 1000 Angstrom units, and is preferably about 300 Angstrom units.
Thicknesses less than about 50 Angstroms, and greater than about 1000 Angstroms, are undesirable ~or the reasons given above~
The thicknesses of the polysilicon and tantalum layers 44 and 52 are dependent on the desired thicknesses of the tantalum silicide and polysilicon layers of the composite structure to be formed in accordance with the inventive fabrication method. The tantalum silicide layer of the composite structure should have a thickness ranging from about 1000 to about 3500 Angstroms r and is preferably about 2500 Angstrom units, while the underlying polysilicon layer (of the composite structure) should have a thickness ranging from abDut 200 to about 6000 Angstrom units, and is preferably about 3500 Angs~rom units. Thicknesses outside these ranges are undesirable for the reasons given above.
In general, in order to produce such a composite structure (after sintering), the polysilicon layer 44 should have a thickness ranging from about 1200 to about 9500 Angstroms while the tantalum layer 52 should have a corresponding thickness ranging from about 400 to about 1400 Angstroms.
A gate-level metallization pattern is foemed in the wafer depicted in FIG. 5 by anisotropically patterning the tantalum and polysilicon layers 52 and 44, in accordance with the inventive reactive ion etching procedure. This patterning is accomplished by depositing a resist 54 (see FIG ~), such as the organic photoresist HPR-204 or the above-described trilevel resist, onto the tantalum layer 52, and delineating a pattern in the resist. Preferably, the pattern delineated in the resist 54 is transerred into the tantalum and polysilicon layers 52 and 44 using the two-step reactive ion etching procedure described ab~ve.
That is, during th~ first step of the two-step etching procedure the tantalum layer 52 and some part, for example, one-half the thickness, of the polysilicon layer 44 i5 reactive ion etched in a plasma containing active etchant fluorine constituents, e.g., a CC13F, CCl2F2, or CClF3 plasma. The resulting structure is shown in FIG. 6.
During the second step of the etching procedure, the remainder of the polysilicon layer 44 is anisotropically reactive ion etched in a plasma containing active etchant chlorine constituents, e.g., a C12 plasma. The structure resulting from this second step is shown in FIG. 7. This two-step etching procedure effectively protects the thin oxide layer 40 against erosion. The range of flow rates, ~2~2~

pressures, and power densities useful in this two-step etching procedure are the same as those described above.
; By way of example, if CC13F gas is ~lowed into the reactor chamber at 25 sccm, if the pressure of the gaseous atmosphere is maintained at 5 millitorr, and if the power density is 0.2 wattstcm2, then the tantalum layer 52 is anisotropically etched at about 2000 Angstrom units per minute.
At the completion of the two s~ep etching procedure, the wafer is removed froM the reactive ion etching chamber and the resist layer 54 is remov d by conventional techniques, e.g., conventional chemical dissolution techniques.
During the final step in the second embodiment of the inventive fabrication process, the processed wafer is sintered in an inert atmosphere, for example, in pure Argon, at about 8Q0 to about 1100 degrees Celsiust and for about 5 to about 120 minutes. Preferably, the sintering is done in pure Argon, at about 900 degrees Celsius for about one hour. This results in the anisotropically patterned tantalum layer 52 and a portion of the anisotropically patterned polysilicon layer 44 chemically combining to form an anisotropically pa~terned tantalum silicide layer 58 overlying an anisotropically patterned layer of pslysilicon 56 (which, in turn, overlies the silicon dioxide film 40), as shown in FIG. 8.
Control samples, similar to the wafer shown in FIG. 5, are used to determine what the appropriate thicknesses of the tantalum layer 52 and the polysilicon layer 44 (see FIG. 5) should be to produce particular desired thicknesses o~ the tantalum silicide layer 58 and the polysilicon layer 56 (see FIG. 8). For example, cross-sectionaL slices of sintered control samples are analyzed by means of transmission electron microscopy to determine the thicknesses o~ the tantalum silicide layer 58 and polysilicon layer 56 resulting from prescribed thicknesses ~CI 25~7 of the tantalum layer 52 and polysilicon layer 44. Using such control samples it has been found, for example, that if, prior to sintering, the patterned tantalum layer 52 had a thickness of about 1000 Angstrom units, and the patterned polys~licon layer 44 had a thickness of about 6000 Angs~rom units, then af~er sin~ering the resulting anisotropically patterned tantalum silicide layer 58 will have a thickness of about 2500 Angstrom uni~s, while the anisotropically patterned polysilicon layer 56 will have a thickness of about 3500 Angstrom units.
In a third embodiment of the inventi~e fabrication method, which is similar to the second embsdiment described above, just the tantalum layer 52, or the tantalum layer 52 and a portion of the polysilicon layer 44, e.g., half the thickness of the polysilicon layer 44, are patterned using, for example, the first step of the two-step etching process described aboveO The resulting structure is shown in FIG. 9. Thereafter, the resist layer 54 is removed and the tantalum and polysilicon layers are sintered, as described above, which results in the formation of a patterned tantalum silicide layer 58 overlying a polysilicon layer 56, which layer 56 is only partially patterned, as shown in FIG. 10. Finally, the remainder of the polysilicon layer 56 is etched in a plasma containing active etchant chlorine constituents, as described above, using the patterned tantal~m silicide layer S8 as an etch mask.
The steps involv~d in the fabrication of a device having low resolution tantalum silicide structures, e.g., low resolution tantalum silicide-on-polysilicon gates, are generally identical to those d~scribed above. While the inven~ive reactive ion etching process described above may be used to do the patterning, conventional plasma etching techniques are also useful. Whichever patterning procedure is used, the resulting devices will be essentially free of conductive etch residues. As emphasized herein, the key to achieving such residue-fre~ devices is to carry out the sintering step needed to produce tantalum silicide after patterning at least the tantalum in such devices.
Finally, it is to be understood that the above-described techniques are only illustrative of theprinciples of the present invention. In accordance with these principles, numerous modificatlons and alternatives may be devised by those skilled in the art without departing from the spirit and soope of the invention.
10 ~
The first embodiment of the inventive fabrication method was used to form an aniso~ropically patterned, composite layer of silicon-rich tantalum silicide-on-polysilicon overlying a silicon dioxide film. The pattern consisted of an array of 2-micron lines and spaces. The workpiece was a 3-inch silicon wafer which had been thermally oxidized to form a layer of SiO2, approximtely 1200 Angstrom units thick, on the surface of the wafer. A
layer of polysilicon, about 3500 Angstrom units thick, had also been deposited onto the oxidized surface of the wafer by conventional low pressure chemical vapor deposition techniques. In addition, a layer of an amorphous mixture of tantalum and silicon, about 2500 Angstrom units thick, had been deposited onto the layer of polysilicon by co-sputtering tantalum and silicon onto the polysilicon layer rom separate tantalum and silicon targetsO The sputter rates of the tantalum and silicon were controlled to produce an atomic ratio of silicon to tantalum of about 2.2.
The first embodiment of the inventive fabrication method was initiated by spinning a l~m thick layer of HPR-204 photoresist onto the layer of the amorphous mixture of tantalum and silicon, which photoresist was purchased from the Philip A. Hunt Chemical Corporation of Palisades Park~ New Jersey. The photoresist was baked for about 20 min~l~es at about 90 degrees Celsius. A pattern of 2-micron lines and spaces was then defined in the photoresist by exposing the photoresist to W light (wavelength equal to 3100 Angstroms) through a mask, and then developing the resist with a wet developer which is sold under the trade name ~SI Developex by the Philip A.
Hunt Chemical Corporation. The photoresist was a~ain baked for about 30 minutes at a~out 1~0 degrees Celsius.
The workpiece was then placed on the power elec~rode of a parallel pla~e, reactive ion etching machine of the type described above, which power elQctrode constituted the cathode of the machine. The surface o~ the power electrode was circular and had a diameter of about 10 inches~ The spacing between the power electrode and the opposed wall of the grounded reactor chamber, which wall constituted the anode of the machine, was about 6 inches CC13F gas was then flowed into the reactor chamber at 25 sccm, the pressure of the gaseous atmosphere within the reactor chamber was maintained at 5 millitorr, and a 13.56 MHz rf signal was applied to the power electrode to produce a power density of 0.2 watts/cm2. The reactive ion etching wa~ continued for about 3 minutes. This length of time was sufficient, from a prior knowledge o~ the etch rates of the amorphous mixture of tantalum and silicon (about 2000 Angstroms/min.) and the polysilicon (about 1000 Angstroms/min.) in this ~lasma, to etch through the full thickness of the tantalum-and-silicon layer and through about half the thickness of the polysilicon layer.
The reactor chamber was then purged, and the workpiece was then reactive ion etched in the same reactive ion etching machine but in a C12 atmosphere. That is, C12 gas was flowed into the reactor chamber at 15 sccm, the pressure of the gaseous atmosphere within the reactor chamber was maintained at 7 millitorr, and a 13.56 MHz rf signal was applied to the power electrode. The resulting ~Z~
- lg -reactive ion etching of the polysilicon was con~inued for about 2.5 minutes which, from a prior knowledge of the etch rate of polysilicon (about 1000 Angstroms/min.) in the plasma; was known to be sufficient to etch through the remaining thickness of the polysilicon and, in fact, to overetch the polysilicon~
The workpiece was removed from ~he reac~or chamber, and the photoresist was dissolved by the conventional steps of dipping the workpiece for about 10 minu~es into a bath of boiling NH40H, H2O2, and water, rinsing, and again dipping the workpiece for about 10 minutes into ba~h of ~oiling HC1, ~22~ and wa~er. The workpiece was then sintered in an Argon atmosphere at about 900 degrees Celsius for about 30 minutes to form a patterned, composite layer of silicon-rich tantalum silicide-on-polysilicon. From previous analyses, which involved transmission and scanning electron microscopic studies, it was known that the sintering had produced a silicon-rich tantalum silicide layer about 2300 Angstrom units thick overlying a polysilicon layer about 3500 Angstrom units thick.
Cleaved samples of the workpiece were then placed in a scanning electron microscope~ and scanning electron micrographic photographs were taken. The photographs showed that the walls OL the etch pits in the composite layer o~ tantalum silicide-on-polysilicon were essentially vertical. In addition~ the photographs showed no observable etch residues within the etch pits.
Exam~le 2 The second embodiment of the inventive fabrication method was also used to form an anisotropically pat~erned, composite layer oE tantalum silicide-on-polysilicon over-lying a silicon dioxide film. The pat~ern also consisted of an array of 2-micron lines and spaces. The workpiece was a 3-inch silicon wafer which had been thermally 5~7 oxidized to orm a layer of SiO2, approximately 120~
~ngstrom units thick, on the surface of the wa~er~ In addition, a layer of polysilicon, about 6000 Angstrom u~its thick, had been deposited onto the oxidized surface 5 of the wafer by conventional low pressure chemical vapor deposition techniques, and a layer of tantalum, about 1000 Angstrom units ~hick, had been sputter deposited onto the polysilicon.
The second embodiment of the inventive fabrication method was initiated by spinning a l~m-thick layer of HP~-204 photoresist onto the tantalum layer. A pattern of 2-micron lines and spaces was then defined in the photo-resist by p~ebaking the resist, by exposing ~he resist to W light through a mask, developing the resist, and then postbaking the resist, as in Example 1.
The workpiece was then placed on the power electrode of the parallel plate, reactive ion etching machine described in Example 1, and then etched in the CC13F
plasma described in Example 1. The reac~ive ion etching ~0 was continued for 3 1/2 minutes. Th;s length of time was sufficient, from a prior knowledge of the etch rates of tantalum (2000 Angstroms/min.) and polysilicon ~1000 Angstroms/min.) in this plasma to etch through the full thickness of the tantalum layer and through about half the thickness of the polysilicon.
The reactor chamber was then purged, and the workpiece was then reactive ion etched in the C12 plasma described in Example 1. The reactive ion etching of the polysilicon was continued for about 4 minutes which, from a prior knowledge of the etch rate of the polysilicon (1000 Angstroms/min.) in this plasma, was known to be sufficient to etch through the remaining thickness of the polysilicon.
The workpiece was removed from the r~actor chamber, and the photoresist was chemically dissolved using the pro-cedure described in Example 1. The workpiece was then ~21~Z~

sintered in an Argon atmosphere at about gO0 degrees Celsius ~or about one hour to form a patterned, composite layer of ~antalum silicide-on-polysilicon. From previous analyses, which involved transmission and scanning electron S microscopic studies, it was known that the sintering procedure had produced a tantalum 5il icide layer about 2500 Angstrom units thick overlying a polysilicon layer about 3500 Angstrom units thick.
Cleaved samples of the workpiece were then placed in a scanning electron microscope, and scanning electron micro-grahic photographs were taken. The photographs showed that the walls of the etch pits in the composite layer of tantalum silicide-on-polysilicon were essentially vertical.
In addition, the photographs showed no observable etch residues within the etch pits.

Claims (17)

Claims:
1. A method of fabricating a patterned tantalum disilicide structure on a substrate, comprising providing tantalum and silicon on the substrate, first forming a patterned structure comprising said materials by plasma etching tantalum and silicon using an etchant which includes fluorine and chlorine as the predominant etchant species for tantalum and silicon, respectively, and thereafter sintering said structure to convert said materials to tantalum disilicide.
2. The method of claim 1 wherein said structure is formed using an anisotropic patterning process.
3. The method of claim 1 wherein said tantalum and silicon are provided on said substrate in the form of a layer containing an amorphous mixture of tantalum and silicon.
4. The method of claim 3 wherein said layer is patterned by reactive ion etching said layer in a plasma which comprises active etchant radicals that include fluorine and chlorine constituents as etching species.
5. The method of claim 4 wherein said plasma is established in a gaseous atmosphere which includes a gas selected from the group consisting of CC13F, CC12F2, and CC1F3.
6. The method of claim 5 wherein said reactive ion etching is accomplished by mounting said device on a driven electrode of a reactive ion etching apparatus, flowing said gas into said apparatus at a flow rate in the range 5 to 100 standard cubic centimeters per minute, maintaining the power density in the range 0.05 to 1.0 watts per square centimeter.
7. The method of claim 6 wherein said flow rate is in the range 10 to 25 standard cubic centimeters per minute, said pressure is in the range 4 to 20 millitorr, and said power density is in the range 0.15 to 0.4 watts per square centimeter.
8. The method of claim 3 wherein said substrate includes a layer of polysilicon onto which said layer is deposited.
9. The method of claim 8 wherein said step of forming said structure includes the step of patterning said layer of polysilicon.
10. The method of claim 9 wherein at least a portion of said polysilicon layer is patterned by reactive ion etching said polysilicon layer in a plasma which comprises active etchant radicals that include chlorine constitutents as etching species.

Claims Supported by the Supplementary Disclosure
11. A method of forming a patterned layer of tantalum disilicide on a substrate comprising providing the materials tantalum and silicon on the substrate, patterning at least said tantalum, and then reacting said tantalum with said silicon to form said patterned tantalum disilicide layer.
12. The method of claim 11 wherein said tantalum and silicon are deposited as successive layers of polysilicon and tantalum, and said patterning step includes the steps of patterning said tantalum and polysilicon layers.
13. The method of claim 11 wherein said tantalum and silicon are deposited as successive layers of polysilicon and tantalum, and said patterning step includes the step of patterning said layer of tantalum.
14. The method of claim 13 wherein said step of patterning said layer of tantalum includes the step of patterning a portion of said polysilicon layer.
15. The method of claim 13 wherein said sintering step reacts the tantalum and polysilicon layers to form a patterned layer of tantalum silicide overlying an unreacted layer of polysilicon.
16. The method of claim 15 further comprising the step of patterning the unreacted layer of polysilicon.
17. The method of claim 12 wherein said layer of tantalum is patterned by reactive ion etching said layer in a plasma which comprises active etchant radicals that include fluorine constituents as etching species.
CA000401014A 1981-05-22 1982-04-15 Reactive ion layers containing tantalum and silicon Expired CA1202597A (en)

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DE3216823A1 (en) * 1982-05-05 1983-11-10 Siemens Ag A process for the manufacture of structures containing from group consisting of metal silicide and polysilicon bilayers in integrated semiconductor circuits by reactive ion etching substrates
US4414057A (en) * 1982-12-03 1983-11-08 Inmos Corporation Anisotropic silicide etching process
DE3315719A1 (en) * 1983-04-29 1984-10-31 Siemens Ag A process for the manufacture of metal silicides of structures from or polycide existing double layers for integrated semiconductor circuits by reactive ion etching
US4528066A (en) * 1984-07-06 1985-07-09 Ibm Corporation Selective anisotropic reactive ion etching process for polysilicide composite structures
NL8500771A (en) * 1985-03-18 1986-10-16 Philips Nv A method of manufacturing a semiconductor device in which a on a layer of silicon oxide contained double layer - consisting of poly Si and a silicide - is etched in a plasma.
EP0229104A1 (en) * 1985-06-28 1987-07-22 AT&T Corp. Procedure for fabricating devices involving dry etching
DE4114741C2 (en) * 1990-07-04 1998-11-12 Mitsubishi Electric Corp Method for forming a printed conductor on a semiconductor substrate
US6177337B1 (en) * 1998-01-06 2001-01-23 International Business Machines Corporation Method of reducing metal voids in semiconductor device interconnection

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