FR2506519A1 - Procede d'attaque ionique reactive de couches contenant du tantale et du silicium - Google Patents

Procede d'attaque ionique reactive de couches contenant du tantale et du silicium

Info

Publication number
FR2506519A1
FR2506519A1 FR8208669A FR8208669A FR2506519A1 FR 2506519 A1 FR2506519 A1 FR 2506519A1 FR 8208669 A FR8208669 A FR 8208669A FR 8208669 A FR8208669 A FR 8208669A FR 2506519 A1 FR2506519 A1 FR 2506519A1
Authority
FR
France
Prior art keywords
attack
layer
polycrystalline silicon
silicon
reactive ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8208669A
Other languages
English (en)
Other versions
FR2506519B1 (fr
Inventor
Jean Serge Deslauriers
Hyman Joseph Levinstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of FR2506519A1 publication Critical patent/FR2506519A1/fr
Application granted granted Critical
Publication of FR2506519B1 publication Critical patent/FR2506519B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'INVENTION CONCERNE LA TECHNOLOGIE DES SEMICONDUCTEURS. UNE METALLISATION DE NIVEAU DE GRILLE A FAIBLE RESISTIVITE POUR DES DISPOSITIFS MOS A TRES HAUT NIVEAU D'INTEGRATION COMPREND UNE STRUCTURE COMPOSITE A DEUX COUCHES 44, 46 DU TYPE TASI SUR SILICIUM POLYCRISTALLIN, RECOUVRANT UNE COUCHE D'OXYDE DE GRILLE RELATIVEMENT MINCE 40. CONFORMEMENT A L'INVENTION, ON EFFECTUE UNE ATTAQUE ANISOTROPE DE LA STRUCTURE COMPOSITE PAR UN TRAITEMENT D'ATTAQUE IONIQUE REACTIVE EN DEUX ETAPES. ON UTILISE LE GAZ CCLF POUR ATTAQUER LA COUCHE DE TASI ET UNE PARTIE DE LA COUCHE DE SILICIUM POLYCRISTALLIN, PUIS LE GAZ CL POUR ATTAQUER LE SILICIUM POLYCRISTALLIN RESTANT. APPLICATION A LA FABRICATION DE CIRCUITS MOS.
FR828208669A 1981-05-22 1982-05-18 Procede d'attaque ionique reactive de couches contenant du tantale et du silicium Expired FR2506519B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26643381A 1981-05-22 1981-05-22

Publications (2)

Publication Number Publication Date
FR2506519A1 true FR2506519A1 (fr) 1982-11-26
FR2506519B1 FR2506519B1 (fr) 1985-07-26

Family

ID=23014579

Family Applications (1)

Application Number Title Priority Date Filing Date
FR828208669A Expired FR2506519B1 (fr) 1981-05-22 1982-05-18 Procede d'attaque ionique reactive de couches contenant du tantale et du silicium

Country Status (8)

Country Link
JP (1) JPS57198633A (fr)
BE (1) BE893251A (fr)
CA (1) CA1202597A (fr)
DE (1) DE3219284A1 (fr)
FR (1) FR2506519B1 (fr)
GB (1) GB2098931B (fr)
IT (1) IT1151209B (fr)
NL (1) NL8202103A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3216823A1 (de) * 1982-05-05 1983-11-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsilizid und polysilizium bestehenden doppelschichten auf integrierte halbleiterschaltungen enthaltenden substraten durch reaktives ionenaetzen
US4414057A (en) * 1982-12-03 1983-11-08 Inmos Corporation Anisotropic silicide etching process
DE3315719A1 (de) * 1983-04-29 1984-10-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsiliziden bzw. silizid-polysilizium bestehenden doppelschichten fuer integrierte halbleiterschaltungen durch reaktives ionenaetzen
US4528066A (en) * 1984-07-06 1985-07-09 Ibm Corporation Selective anisotropic reactive ion etching process for polysilicide composite structures
NL8500771A (nl) * 1985-03-18 1986-10-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een op een laag siliciumoxide aanwezige dubbellaag - bestaande uit poly-si en een silicide - in een plasma wordt geetst.
JPS62503204A (ja) * 1985-06-28 1987-12-17 アメリカン テレフオン アンド テレグラフ カムパニ− ドライエッチングを含むデバイスの製作プロセス
DE4114741C2 (de) * 1990-07-04 1998-11-12 Mitsubishi Electric Corp Verfahren zur Bildung einer Leiterbahn auf einem Halbleitersubstrat
US6177337B1 (en) * 1998-01-06 2001-01-23 International Business Machines Corporation Method of reducing metal voids in semiconductor device interconnection

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519873A (en) * 1978-07-28 1980-02-12 Mitsubishi Electric Corp Forming method of metallic layer pattern for semiconductor

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
EXTENDED ABSTRACTS OF THE JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 79, no 2, octobre 1979 ; Princeton, USA G.C. SCHWARTZ et al. "Reactive ion etching of silicon in chlorinated plasmas : a parametric study", resume no. 612, pages 1535-1537 *
EXTENDED ABSTRACTS, vol. 81, no 1, mai 1981 ; Princeton, USA R.S. BENNETT et al. "Polycide etching in a flexible diode reactor", page 750, resume no. 301 *
EXTENTED ABSTRACTS OF THE JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 80, no 2, octobre 1980 ; Princeton, USA F.R. WHITE et al. "Plasma etching of composite silicide gate electrodes", resume no. 330, pages 854-855 *
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 128, no 3, mars 1981 ; Manchester, USA R.S. BENNETT et al. "Polycide etching in a flexible diode reactor", page 105C, resume no. 301 *

Also Published As

Publication number Publication date
FR2506519B1 (fr) 1985-07-26
BE893251A (fr) 1982-09-16
GB2098931B (en) 1985-02-06
DE3219284A1 (de) 1982-12-16
IT1151209B (it) 1986-12-17
GB2098931A (en) 1982-12-01
DE3219284C2 (fr) 1989-08-10
CA1202597A (fr) 1986-04-01
JPS57198633A (en) 1982-12-06
IT8221430A0 (it) 1982-05-21
NL8202103A (nl) 1982-12-16

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Legal Events

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