IT1151209B - Procedimento per la fabbricazione di un dispositivo a semiconduttori - Google Patents
Procedimento per la fabbricazione di un dispositivo a semiconduttoriInfo
- Publication number
- IT1151209B IT1151209B IT21430/82A IT2143082A IT1151209B IT 1151209 B IT1151209 B IT 1151209B IT 21430/82 A IT21430/82 A IT 21430/82A IT 2143082 A IT2143082 A IT 2143082A IT 1151209 B IT1151209 B IT 1151209B
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- manufacture
- semiconductor device
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
- H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
- H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
- H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
- H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
- H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
- H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26643381A | 1981-05-22 | 1981-05-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| IT8221430A0 IT8221430A0 (it) | 1982-05-21 |
| IT1151209B true IT1151209B (it) | 1986-12-17 |
Family
ID=23014579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT21430/82A IT1151209B (it) | 1981-05-22 | 1982-05-21 | Procedimento per la fabbricazione di un dispositivo a semiconduttori |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS57198633A (https=) |
| BE (1) | BE893251A (https=) |
| CA (1) | CA1202597A (https=) |
| DE (1) | DE3219284A1 (https=) |
| FR (1) | FR2506519B1 (https=) |
| GB (1) | GB2098931B (https=) |
| IT (1) | IT1151209B (https=) |
| NL (1) | NL8202103A (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3216823A1 (de) * | 1982-05-05 | 1983-11-10 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von strukturen von aus metallsilizid und polysilizium bestehenden doppelschichten auf integrierte halbleiterschaltungen enthaltenden substraten durch reaktives ionenaetzen |
| US4414057A (en) * | 1982-12-03 | 1983-11-08 | Inmos Corporation | Anisotropic silicide etching process |
| DE3315719A1 (de) * | 1983-04-29 | 1984-10-31 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von strukturen von aus metallsiliziden bzw. silizid-polysilizium bestehenden doppelschichten fuer integrierte halbleiterschaltungen durch reaktives ionenaetzen |
| US4528066A (en) * | 1984-07-06 | 1985-07-09 | Ibm Corporation | Selective anisotropic reactive ion etching process for polysilicide composite structures |
| NL8500771A (nl) * | 1985-03-18 | 1986-10-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een op een laag siliciumoxide aanwezige dubbellaag - bestaande uit poly-si en een silicide - in een plasma wordt geetst. |
| EP0229104A1 (en) * | 1985-06-28 | 1987-07-22 | AT&T Corp. | Procedure for fabricating devices involving dry etching |
| DE4114741C2 (de) * | 1990-07-04 | 1998-11-12 | Mitsubishi Electric Corp | Verfahren zur Bildung einer Leiterbahn auf einem Halbleitersubstrat |
| US6177337B1 (en) * | 1998-01-06 | 2001-01-23 | International Business Machines Corporation | Method of reducing metal voids in semiconductor device interconnection |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5519873A (en) * | 1978-07-28 | 1980-02-12 | Mitsubishi Electric Corp | Forming method of metallic layer pattern for semiconductor |
-
1982
- 1982-04-15 CA CA000401014A patent/CA1202597A/en not_active Expired
- 1982-05-18 GB GB8214402A patent/GB2098931B/en not_active Expired
- 1982-05-18 FR FR828208669A patent/FR2506519B1/fr not_active Expired
- 1982-05-19 BE BE0/208144A patent/BE893251A/fr not_active IP Right Cessation
- 1982-05-20 JP JP57084147A patent/JPS57198633A/ja active Pending
- 1982-05-21 IT IT21430/82A patent/IT1151209B/it active
- 1982-05-21 NL NL8202103A patent/NL8202103A/nl not_active Application Discontinuation
- 1982-05-22 DE DE19823219284 patent/DE3219284A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE3219284A1 (de) | 1982-12-16 |
| DE3219284C2 (https=) | 1989-08-10 |
| GB2098931A (en) | 1982-12-01 |
| FR2506519A1 (fr) | 1982-11-26 |
| FR2506519B1 (fr) | 1985-07-26 |
| BE893251A (fr) | 1982-09-16 |
| JPS57198633A (en) | 1982-12-06 |
| IT8221430A0 (it) | 1982-05-21 |
| NL8202103A (nl) | 1982-12-16 |
| GB2098931B (en) | 1985-02-06 |
| CA1202597A (en) | 1986-04-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970526 |